An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

Hardware-software interaction testing is performed using formal verification for language-specified hardware designs. A description of valid access using an interface for a configuration space of a language specified hardware design and a description of a valid output of the language-specified hardware design is received. Formal verification is performed on the language-specified hardware design using the interface for the configuration space according to the description of valid access using the interface. A sequence of access to the configuration space using the interface that causes a failure to produce the valid output of the language-specified hardware design according to the description of valid output to identify as an error for the language-specified hardware design.

Hardware-software interaction testing is performed using formal verification for language-specified hardware designs. A description of valid access using an interface for a configuration space of a language specified hardware design and a description of a valid output of the language-specified hardware design is received. Formal verification is performed on the language-specified hardware design using the interface for the configuration space according to the description of valid access using the interface. A sequence of access to the configuration space using the interface that causes a failure to produce the valid output of the language-specified hardware design according to the description of valid output to identify as an error for the language-specified hardware design.

The present disclosure relates to a system and method for electronic design. Embodiments may include receiving, using at least one processor, a plurality of distinct electronic designs at an electronic design database and storing the plurality of distinct electronic designs at the electronic design database. Embodiments may further include receiving a request to reuse one of the plurality of distinct electronic designs from a client electronic device associated with a user, wherein the request includes design connectivity information, block connectivity information, and page connectivity information. Embodiments may also include analyzing the design connectivity information, block connectivity information, and page connectivity information to identify one or more closest matches with the plurality of distinct electronic designs and providing the one or more closest matches to the client electronic device to allow for subsequent displaying at a graphical user interface.

The present disclosure relates to a system and method for electronic design. Embodiments may include receiving, using at least one processor, a plurality of distinct electronic designs at an electronic design database and storing the plurality of distinct electronic designs at the electronic design database. Embodiments may further include receiving a request to reuse one of the plurality of distinct electronic designs from a client electronic device associated with a user, wherein the request includes design connectivity information, block connectivity information, and page connectivity information. Embodiments may also include analyzing the design connectivity information, block connectivity information, and page connectivity information to identify one or more closest matches with the plurality of distinct electronic designs and providing the one or more closest matches to the client electronic device to allow for subsequent displaying at a graphical user interface.

Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of different floorplans are executed using the circuit architecture in the IC. The plurality of PPG circuit blocks mimic the memory access patterns of the kernels for each of the plurality of different floorplans during the executing. One or more design constraints are generated based on a selected floorplan. The selected floorplan is selected from the plurality of different floorplans based on one or more performance metrics determined from the executing.

Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of different floorplans are executed using the circuit architecture in the IC. The plurality of PPG circuit blocks mimic the memory access patterns of the kernels for each of the plurality of different floorplans during the executing. One or more design constraints are generated based on a selected floorplan. The selected floorplan is selected from the plurality of different floorplans based on one or more performance metrics determined from the executing.

Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.