A simulator can simulate a circuit design describing an electronic device using a single processing device of a computing system. The simulator can generate profile data associated with compilation of the circuit design and the single processing device simulation of the compiled circuit design. The profile data can identify multiple different ways to partition the circuit design and include information corresponding to the single processing device simulation of the compiled circuit design. A parallel simulation qualifier can determine a parallelism factor corresponding to an expected performance of the computing system in a multiple processing device simulation of the circuit design based on the profile data from the single processing device simulation of the circuit design. The simulator can utilize the parallelism factor to partition the circuit design in one of the different ways, and simulate the partitioned circuit design with multiple processing devices of the computing system.

The present disclosure describes various embodiments of systems, apparatuses, and methods for detecting a Trojan inserted integrated circuit design using delay-based side channel analysis. In one such embodiment, an automated test generation algorithm produces test patterns that are likely to activate trigger conditions and change critical paths of an integrated circuit design.

The present disclosure describes various embodiments of systems, apparatuses, and methods for detecting a Trojan inserted integrated circuit design using delay-based side channel analysis. In one such embodiment, an automated test generation algorithm produces test patterns that are likely to activate trigger conditions and change critical paths of an integrated circuit design.

The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving one or more user defined processor configurations at a processor generator. Embodiments may also include generating a customized testbench based upon, at least in part, the user defined processor configurations and generating an RTL model while the customized testbench is generating.

Learning-based power modeling of a processor core includes generating, using computer hardware, pipeline snapshot data specifying a plurality of snapshots for a pipeline of a processor core. Each snapshot specifies a state of the pipeline for a clock cycle in executing a computer program over a plurality of clock cycles. A plurality of estimates of power consumption for the processor core in executing the computer program for the plurality of clock cycles are determined, using an instruction-based power model executed by the computer hardware, a based on the pipeline snapshot data. The plurality of estimates of power consumption are calculated using the instruction-based power model based on the plurality of snapshots over the plurality of clock cycles.

The present invention pertains to a method of verifying a design of an integrated circuit. The methods executes an iteration of simulation test cycle using a digital representation of the design. Next, the method obtains simulation results from the iteration of the simulation test cycle and calculates, during the simulation test cycle, a test coverage value associated with the simulation results of the iteration of the simulation test cycle. If the test coverage value is less than a target value, the method determines if the simulation test cycle fails to satisfies an iteration limiting metric. If the simulation test cycle satisfies the iteration limiting metric, the method, dynamically adjusts one or more simulation test cycle parameter during the simulation test cycle and iterates the simulation test cycle and recalculating the test coverage value until the test coverage value is at least the target value or the simulation test cycle fails to satisfy the iteration limiting metric. The method then out puts a result of the verification of the design.

The present invention pertains to a method of verifying a design of an integrated circuit. The methods executes an iteration of simulation test cycle using a digital representation of the design. Next, the method obtains simulation results from the iteration of the simulation test cycle and calculates, during the simulation test cycle, a test coverage value associated with the simulation results of the iteration of the simulation test cycle. If the test coverage value is less than a target value, the method determines if the simulation test cycle fails to satisfies an iteration limiting metric. If the simulation test cycle satisfies the iteration limiting metric, the method, dynamically adjusts one or more simulation test cycle parameter during the simulation test cycle and iterates the simulation test cycle and recalculating the test coverage value until the test coverage value is at least the target value or the simulation test cycle fails to satisfy the iteration limiting metric. The method then out puts a result of the verification of the design.

A method for determining a deformation of a resist in a patterning process. The method involves obtaining a resist deformation model of a resist having a pattern, the resist deformation model configured to simulate a fluid flow of the resist due to capillary forces acting on a contour of at least one feature of the pattern; and determining, via the resist deformation model, a deformation of a resist pattern to be developed based on an input pattern to the resist deformation model.

A method for determining a deformation of a resist in a patterning process. The method involves obtaining a resist deformation model of a resist having a pattern, the resist deformation model configured to simulate a fluid flow of the resist due to capillary forces acting on a contour of at least one feature of the pattern; and determining, via the resist deformation model, a deformation of a resist pattern to be developed based on an input pattern to the resist deformation model.

A highly parallelized parallel tempering technique for simulating dynamic systems, such as quantum processors, is provided. Replica exchange is facilitated by synchronizing grid-level memory. Particular implementations for simulating quantum processors by representing cells of qubits and couplers in grid-, block-, and thread-level memory are discussed. Parallel tempering of such dynamic systems can be assisted by modifying replicas based on isoenergetic cluster moves (ICMs). ICMs are generated via secondary replicas which are maintained alongside primary replicas and exchanged between blocks and/or generated dynamically by blocks without necessarily being exchanged. Certain refinements, such as exchanging energies and temperatures through grid-level memory, are also discussed.