The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving one or more user defined processor configurations at a processor generator. Embodiments may also include generating a customized testbench based upon, at least in part, the user defined processor configurations and generating an RTL model while the customized testbench is generating.

An apparatus includes a core logic circuit, one or more integrated clock-gating (ICG) cells, and one or more ICG control cells (ICCs). The core logic circuit generally comprises a plurality of flip-flops. The plurality of flip-flops may be connected to form one or more scan chains. Each of the one or more integrated clock-gating (ICG) cells may be configured to gate a clock signal of a respective one of the one or more scan chains. Each of the one or more ICG control cells may be configured to control a respective one or more of the one or more ICG cells.

An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. The local control circuit retrieves data stored in the user storage circuits through the scan storage circuits without erasing the data stored in the user storage circuits after halting oscillations in a user clock signal that clocks the user storage circuits. The local control circuit restarts oscillations in the user clock signal after the data is provided from the user storage circuits to the scan storage circuits.

Some embodiments of the invention relate to generating correction information based on global or regional navigation satellite system (NSS) multiple-frequency signals observed at a network of reference stations, broadcasting the correction information, receiving the correction information at one or more monitoring stations, estimating ambiguities in the carrier phase of the NSS signals observed at the monitoring station(s) using the correction information received thereat, generating residuals, generating post-broadcast integrity information based thereon, and broadcasting the post-broadcast integrity information. Other embodiments relate to receiving and processing correction information and post-broadcast integrity information at NSS receivers or at devices which may have no NSS receiver, as well as to systems, NSS receivers, devices which may have no NSS receiver, processing centers, and computer programs. Some embodiments may for example be used for safety-critical applications such as highly-automated driving and autonomous driving.

Some embodiments of the invention relate to generating correction information based on global or regional navigation satellite system (NSS) multiple-frequency signals observed at a network of reference stations, broadcasting the correction information, receiving the correction information at one or more monitoring stations, estimating ambiguities in the carrier phase of the NSS signals observed at the monitoring station(s) using the correction information received thereat, generating residuals, generating post-broadcast integrity information based thereon, and broadcasting the post-broadcast integrity information. Other embodiments relate to receiving and processing correction information and post-broadcast integrity information at NSS receivers or at devices which may have no NSS receiver, as well as to systems, NSS receivers, devices which may have no NSS receiver, processing centers, and computer programs. Some embodiments may for example be used for safety-critical applications such as highly-automated driving and autonomous driving.

A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

A vehicle can capture data that can be converted into a synthetic scenario for use in a simulator. Objects can be identified in the data and attributes associated with the objects can be determined. The data can be used to generate a synthetic scenario of a simulated environment. The scenarios can include simulated objects that traverse the simulated environment and perform actions based on the attributes associated with the objects, the captured data, and/or interactions within the simulated environment. In some instances, the simulated objects can be filtered from the scenario based on attributes associated with the simulated objects and can be instantiated and/or destroyed based on triggers within the simulated environment. The scenarios can be used for testing and validating interactions and responses of a vehicle controller within the simulated environment.

A vehicle can capture data that can be converted into a synthetic scenario for use in a simulator. Objects can be identified in the data and attributes associated with the objects can be determined. The data can be used to generate a synthetic scenario of a simulated environment. The scenarios can include simulated objects that traverse the simulated environment and perform actions based on the attributes associated with the objects, the captured data, and/or interactions within the simulated environment. In some instances, the simulated objects can be filtered from the scenario based on attributes associated with the simulated objects and can be instantiated and/or destroyed based on triggers within the simulated environment. The scenarios can be used for testing and validating interactions and responses of a vehicle controller within the simulated environment.

Apparatus and associated methods relate to generating a wiring schema with more than one safety device sharing at least one test signal through one or more external terminal blocks when the number of terminals required by safety devices exceeds the number of available terminals of a safety controller. In an illustrative example, the method may include determining a total number of terminals A of safety devices to be connected to a safety evaluation device having a number of terminals B. If A is greater than B, the method may then include generating a wiring schema that one or more external terminal blocks may show indicia of electrical connections between an identified set of safety devices and a shared terminal of the safety evaluation device associated with that set. Various embodiments may advantageously expand a number of devices to be connected to the safety evaluation device.

The present invention discloses a detection method, a system, an electronic equipment, and a storage medium of product test data, where the detection method includes: obtaining historical test data of historical batches of products; screening the historical test data to obtain intermediate test data; grouping the intermediate test data based on preset test parameters to obtain first groups; obtaining distribution patterns of the first groups based on the intermediate test data of the first groups; when the distribution pattern is a preset distribution pattern, using the first group corresponding to the distribution pattern as a target group; and obtaining a target test limit value based on the intermediate test data corresponding to the target group. In the present invention, the test limit value can be adjusted dynamically and adaptively, and chip test data with abnormal data can be effectively detected in real time, which improves test quality of the chip.