A hardware architecture for implementing a convolutional neural network.

A hardware architecture for implementing a convolutional neural network.

An DNN accelerator can perform fixed-point emulation of floating-point computation. In a multiplication operation on two floating-point matrices, the DNN accelerator determines an extreme exponent for a row in the first floating-point matrix and determines another extreme exponent for a column in the second floating-point matrix. The row and column can be converted to fixed-point vectors based on the extreme exponents. The two fixed-point vectors are fed into a PE array in the DNN accelerator. The PE array performs a multiplication operation on the two fixed-point vectors and generates a fixed-point inner product. The fixed-point inner product can be converted back to a floating-point inner product based on the extreme exponents. The floating-point inner product is an element in the matrix resulted from the multiplication operation on the two floating-point matrices. The matrix can be accumulated with another matrix resulted from a fixed-point emulation of a floating-point matrix multiplication.

Methods and systems related to the efficient execution of complex computations by a multicore processor and the movement of data among the various processing cores in the multicore processor are disclosed. A multicore processor includes a set of processing cores and associated sets of processing pipelines, core controllers, routers, and network interface units. The multicore processor also includes a computation layer, for conducting computations using the set of processing cores, with executable instructions for the set of processing pipelines which are executed by the set of core controllers. The multicore processor also includes a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for the set of routers and the set of network interface units. The multicore processor also includes a set of programmable controllers, with executable instructions for reformatting computational data from the computation layer for transmission through the network-on-chip layer.

Mechanisms can be designed to manage non-contact forces to reduce energy consumption and/or to control interactions between the parts. Management of non-contact forces is especially useful in micro-scale and nano-scale mechanisms, where van der Waals attraction between parts of the mechanism may be significant to the operation of the mechanism.

A computer-implemented method to establish a relative importance of an input parameter p.sub.j in a plurality of input parameters p.sub.i in a data set input to a machine learning model, the data set represented by a j row by k column matrix I.sub.m, an intersection of each row with each column defining an element, the method includes for each of the plurality of parameters p.sub.i in the input data set, a computer sorts columns k.sub.i of the matrix I.sub.m. to produce a re-ordered matrix I.sub.m,j; the computer determines a hyper-parameter N* of sub-matrices into which may be sorted the values in a j.sup.th row of the re-ordered matrix I.sub.m,j; the computer generates a plurality of group sub-matrices G.sub.i, each of the group sub-matrices comprising a subset of columns and the jth row; the computer inputs the re-ordered matrix I.sub.m,j into a fully-trained machine learning model to produce machine learning model outputs; and the computer produces normalized mean values of the outputs.

A computer-implemented method to establish a relative importance of an input parameter p.sub.j in a plurality of input parameters p.sub.i in a data set input to a machine learning model, the data set represented by a j row by k column matrix I.sub.m, an intersection of each row with each column defining an element, the method includes for each of the plurality of parameters p.sub.i in the input data set, a computer sorts columns k.sub.i of the matrix I.sub.m. to produce a re-ordered matrix I.sub.m,j; the computer determines a hyper-parameter N* of sub-matrices into which may be sorted the values in a j.sup.th row of the re-ordered matrix I.sub.m,j; the computer generates a plurality of group sub-matrices G.sub.i, each of the group sub-matrices comprising a subset of columns and the jth row; the computer inputs the re-ordered matrix I.sub.m,j into a fully-trained machine learning model to produce machine learning model outputs; and the computer produces normalized mean values of the outputs.

An interaction prediction system for accurately predicting the occurrence of interactions, entities associated with the interactions, and/or resources involved with the interactions. The interaction predictions can be used for a number of different purposes, such as improving security of systems, predicting future interactions or the likelihood thereof, or the like. The interaction prediction system described herein more accurately predict the interactions using modeling and monitoring that increases the processing speeds by reducing the data needed to make the predictions, reduces the memory requirements to make the predictions, and increases the capacity of the processing systems when compared to traditional systems.

An interaction prediction system for accurately predicting the occurrence of interactions, entities associated with the interactions, and/or resources involved with the interactions. The interaction predictions can be used for a number of different purposes, such as improving security of systems, predicting future interactions or the likelihood thereof, or the like. The interaction prediction system described herein more accurately predict the interactions using modeling and monitoring that increases the processing speeds by reducing the data needed to make the predictions, reduces the memory requirements to make the predictions, and increases the capacity of the processing systems when compared to traditional systems.

Systems, apparatuses, and methods related to acceleration circuitry are described. The acceleration circuitry may be deployed in a memory device and can include a memory resource and/or logic circuitry. The acceleration circuitry can perform operations on data to convert the data between one or more numeric formats, such as floating-point and/or universal number (e.g., posit) formats. The acceleration circuitry can perform arithmetic and/or logical operations on the data after the data has been converted to a particular format. For instance, the memory resource can receive data comprising a bit string having a first format that provides a first level of precision. The logic circuitry can receive the data from the memory resource and convert the bit string to a second format that provides a second level of precision that is different from the first level of precision.