Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct memory access engine by a second direct memory access engine to the data processing device via the second direct memory access engine is disclosed.

A system and method for efficiently processing and managing data stored in a queue. A processing device may process the data stored in the queue. Queue protocols can be applied to the queue to efficiently process and manage data stored in the queue. Queue protocols may facilitate efficient use of processing resources that process the data stored in one or more queues. A queue protocol may include at least a first protocol for facilitating transfer of data in the queue to another queue processed by another processing device or a second protocol for inhibiting transfer of data in the queue to another queue.

An imaging apparatus including a frame buffer executes high-speed shooting consecutively in plural sessions. An imaging element includes a buffer, an image producing unit, a managing unit, and an output unit. The image producing unit produces an image in the case where an empty capacity of any of plural areas in the buffer exceeds a predetermined threshold value. The managing unit causes an area whose empty capacity exceeds the predetermined threshold value, of the plural areas to retain the image as a buffering image. The output unit extracts the buffering image from the buffer and outputting the buffering image, in order of the retention of the buffering image.

Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

A group of low-level FIFOs may be logically bound together to form a super-FIFO. The super-FIFO may treat each low-level FIFO as a storage location. The super-FIFO may enable a push to (or a pop from) every low-level FIFO, simultaneously. The super-FIFO may enable a virtual channel (VC) to use the super-FIFO, bypassing a VC FIFO for the VC, removing several cycles of latency otherwise needed for enqueuing and dequeuing messages in the VC FIFO. In addition, the super-FIFO may enable bypassing of an arbiter, further reducing latency by avoiding a penalty of the arbiter.

An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.

The disclosure herein provides systems, methods, and computer program products for managing a plurality of operands in a computer instruction. To manage the plurality of operands, a data buffer manager executed by a processor receives information from a caller. The information relates to the plurality of operands. The data buffer manager, also, compares a free data area size to a requested minimum data area of an operand size identified by the information; selects an address when the requested minimum data area is less than or equal to the free data area size; and inserts the operand at the address.

A physical-layer circuit including a memory, a physical-layer device and a control circuit. The memory receives data from a media access controller (MAC) at a first rate. The MAC is separate from the physical-layer circuit. The physical-layer device receives the data from the memory and transmits the data from the physical-layer circuit to a peer device. The physical-layer device transfers the data from the memory to the peer device at a second rate. An amount of data stored in the memory is based on a difference between the first and second rates. The second rate is less than the first rate. The control circuit is connected between the memory and the physical layer device. The control circuit monitors the amount of the data stored in the memory and, based on the amount of the data stored in the memory, transmits a frame to the MAC to decrease the first rate.

Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

A method for resetting of memory locks in a transactional memory system. The method includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The method further includes determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.