Embodiments include a head-worn display including a display panel sized and positioned to produce a field of view to present digital content to an eye of a user, and a processor adapted to present the digital content to the display panel such that the digital content is only presented in a portion of the field of view, the portion being in the middle of the field of view such that horizontally opposing edges of the field of view are blank areas. The processor is adapted to shift the digital content into one of the blank areas to adjust the convergence distance of the digital content and thereby change the perceived distance from the user to the digital content.

Embodiments include a head-worn display including a display panel sized and positioned to produce a field of view to present digital content to an eye of a user, and a processor adapted to present the digital content to the display panel such that the digital content is only presented in a portion of the field of view, the portion being in the middle of the field of view such that horizontally opposing edges of the field of view are blank areas. The processor is adapted to shift the digital content into one of the blank areas to adjust the convergence distance of the digital content and thereby change the perceived distance from the user to the digital content.

A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

Embodiments include a head-worn display including a display panel sized and positioned to produce a field of view to present digital content to an eye of a user, and a processor adapted to present the digital content to the display panel such that the digital content is only presented in a portion of the field of view, the portion being in the middle of the field of view such that horizontally opposing edges of the field of view are blank areas. The processor is adapted to shift the digital content into one of the blank areas to adjust the convergence distance of the digital content and thereby change the perceived distance from the user to the digital content.

Embodiments include a head-worn display including a display panel sized and positioned to produce a field of view to present digital content to an eye of a user, and a processor adapted to present the digital content to the display panel such that the digital content is only presented in a portion of the field of view, the portion being in the middle of the field of view such that horizontally opposing edges of the field of view are blank areas. The processor is adapted to shift the digital content into one of the blank areas to adjust the convergence distance of the digital content and thereby change the perceived distance from the user to the digital content.

The application discloses a buffer device and a method for controlling data access to an internal memory. The buffer device has a central buffer module coupled to a memory interface to receive a command/address signal via a command/address channel. The central buffer module is configured to detect whether a destination address of the received command/address signal is within a predefined address space, and generate a security read/write signal when the command/address signal is within the predefined address space. The buffer device further has a data buffer module coupled between the memory interface and a memory module to buffer data therebetween. The data buffer module is configured to store reference data, compare the buffered data with the reference data in response to the security read/write signal, and determine whether or not to restrict exchange of the buffered data between the memory module and the memory interface.

The application discloses a buffer device and a method for controlling data access to an internal memory. The buffer device has a central buffer module coupled to a memory interface to receive a command/address signal via a command/address channel. The central buffer module is configured to detect whether a destination address of the received command/address signal is within a predefined address space, and generate a security read/write signal when the command/address signal is within the predefined address space. The buffer device further has a data buffer module coupled between the memory interface and a memory module to buffer data therebetween. The data buffer module is configured to store reference data, compare the buffered data with the reference data in response to the security read/write signal, and determine whether or not to restrict exchange of the buffered data between the memory module and the memory interface.

An improved black box data recorder for use with autonomous driving vehicles (AVD). In one embodiment, two cyclic buffers are provided to record vehicle sensors data. A first cyclic buffer records raw vehicle sensor data on a volatile memory, while a second cyclic buffer records the same vehicle sensor data, as compressed data, on a non-volatile memory. In a case of a collision or near collision, in one embodiment the buffers are flushed into a non-volatile (NV) storage for retrieval. As long as there is no power interruption, the raw vehicle sensor data will be accessible from the NV storage. If a power interruption occurs, the raw vehicle sensor data held in the volatile memory of the first cyclic buffer will be lost and only the compressed form of the vehicle sensor data from the second cyclic buffer will survive and be accessible.

A system and method for efficiently processing and managing data stored in a queue. A processing device may process the data stored in the queue. Queue protocols can be applied to the queue to efficiently process and manage data stored in the queue. Queue protocols may facilitate efficient use of processing resources that process the data stored in one or more queues. A queue protocol may include at least a first protocol for facilitating transfer of data in the queue to another queue processed by another processing device or a second protocol for inhibiting transfer of data in the queue to another queue.

Aspects of the present invention relate to methods and systems for the see-through computer display systems with an extended field of view.