Patent classifications
G06F7/06
Device application support
Various example embodiments for providing device application support are presented. In at least some example embodiments, device application support may be configured to support device programmability. In at least some example embodiments, device application support may be configured to support device programmability for enabling a customer that operates a device to develop a customer application for the device and to run the customer application on the device. In at least some example embodiments, device application support may be provided in a manner for enabling a customer to develop and run a customer application for a device without a need for the customer to use a software development kit (SDK) to develop the customer application.
Technologies for providing shared memory for accelerator sleds
Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.
Technologies for providing shared memory for accelerator sleds
Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.
PERSONALIZED REAL ESTATE EVENT FEED
A personalized feed system is described herein that provides feeds that are tailored to the preferences of each user of a real estate website or application. A user signs up to receive a stored profile with the website, and the profile includes information such as what geographical regions the buyer is interested in, what types of homes the buyer is looking for, and so on. The personalized feed system uses this information to provide a feed specific to the buyer that notifies the buyer of listings that are of particular relevance to that buyer. The personalized feed system summarizes other real estate events that are relevant to the user in a single time-oriented feed. Buyers receive information about new and/or modified listings, sales, outstanding offers, status of a transaction, and the like, while sellers receive information about sales, new and/or modified listings, open offers, and so on.
PERSONALIZED REAL ESTATE EVENT FEED
A personalized feed system is described herein that provides feeds that are tailored to the preferences of each user of a real estate website or application. A user signs up to receive a stored profile with the website, and the profile includes information such as what geographical regions the buyer is interested in, what types of homes the buyer is looking for, and so on. The personalized feed system uses this information to provide a feed specific to the buyer that notifies the buyer of listings that are of particular relevance to that buyer. The personalized feed system summarizes other real estate events that are relevant to the user in a single time-oriented feed. Buyers receive information about new and/or modified listings, sales, outstanding offers, status of a transaction, and the like, while sellers receive information about sales, new and/or modified listings, open offers, and so on.
Tibetan Character Constituent Analysis Method, Tibetan Sorting Method And Corresponding Devices
The present invention discloses a Tibetan character constituent analysis method, a Tibetan sorting method and corresponding devices, and relates to the field of natural language processing. The present invention is proposed to solve the problem that the existing Tibetan sorting methods have no universality or compatibility, which is inconvenient for the use of automatic computer Tibetan sorting. The technical solution provided by the present invention includes: S10, acquiring a Tibetan text to be analyzed; S20, using Tibetan characters in the Tibetan text as the input of a preset finite state automaton group; and S30, acquiring the constituents of the Tibetan characters according to a target finite state automaton, when the target finite state automaton in the finite state automaton group determines that the Tibetan characters in the Tibetan text are correctly spelled.
KEY-BASED COMPARISON IN NEURAL ENGINE CIRCUIT
Embodiments relate to a neural engine circuit of a neural network processor circuit that performs a parallel sorting operation on input data. The neural engine circuit includes operation circuits and an accumulator circuit coupled to the outputs of the operation circuits. Each of the operation circuits operates in parallel and is configured to compare a field of a first record of a first set of records and a corresponding field of a second record of a second set of records to generate a comparison result on values in the field and the corresponding field. The accumulator circuit includes a record store storing records that are involved in the parallel sorting operation and a sideband register that stores the comparison results generated by the operation circuits.
KEY-BASED COMPARISON IN NEURAL ENGINE CIRCUIT
Embodiments relate to a neural engine circuit of a neural network processor circuit that performs a parallel sorting operation on input data. The neural engine circuit includes operation circuits and an accumulator circuit coupled to the outputs of the operation circuits. Each of the operation circuits operates in parallel and is configured to compare a field of a first record of a first set of records and a corresponding field of a second record of a second set of records to generate a comparison result on values in the field and the corresponding field. The accumulator circuit includes a record store storing records that are involved in the parallel sorting operation and a sideband register that stores the comparison results generated by the operation circuits.
System and method for processing of events
Systems and methods for processing events are disclosed. Event data comprising passive event data, active event data, or both is received. It is determined whether the received event data is available for a pattern of passive event data and active event data. In response to determining that the received event data is available for the pattern of passive event data and active event data, one or more constraints between the passive event data and the active event data are converted into one or more query terms. The query terms are used to construct at least one query. Remaining passive event data that is related to some, but not all, of the active event data is obtained using the constructed at least one query.
Selecting an ith largest or a pth smallest number from a set of n m-bit numbers
A method of selecting, in hardware logic, an i.sup.th largest or a p.sup.th smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the r.sup.th iteration, the method comprises: summing an (m−r).sup.th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the r.sup.th bit of the selected number is determined and output and additionally the (m−r−1).sup.th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m−r).sup.th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.