A method, computer program product, and a computer system are disclosed for processing information using hardware instructions in a processor of a computer system by performing a hardware reduction instruction using an input to calculate at least one range reduction factor of the input; performing a hardware restoration instruction using the input to calculate at least one range restoration factor of the input; and performing a final fused multiply add (FMA) type of hardware instruction or a multiply (FM) hardware instruction by combining an approximation based on a value reduced by the at least one range reduction factor with the at least one range restoration factor.

A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. The tiles can be arranged in an array or grid and can be communicatively coupled. In an example, the tiles can be arranged in a one-dimensional array and each tile can be coupled to its respective adjacent neighbor tiles using a direct bus coupling. Each tile can be further coupled to at least one non-adjacent neighbor tile that is one tile, or device space, away using a passthrough bus. The passthrough bus can extend through intervening tiles.

Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.

A multi-addend adder circuit used for multi-addend addition in a polar representation in stochastic computing. The multi-addend adder circuit includes a buffer circuit and a computing circuit, where the buffer circuit is configured to store to-be-buffered data for at least one cycle and output buffer data, and the computing circuit is configured to process a plurality of pieces of bitstream data and the buffer data and output one piece of bitstream data and the to-be-buffered data, where the piece of output bitstream data is a quotient of dividing a sum of summation data and the buffer data by a scale-down coefficient, the output to-be-buffered data is a remainder of dividing a sum of all summation data until a current cycle by the scale-down coefficient, and the summation data is a quantity of bits whose values are 1 in the plurality of pieces of first bitstream data.

A microprocessor for metering electric energy, a microcontroller unit thereof, and a circuit and a method for metering energy accumulation. The circuit for metering energy accumulation includes a calculation-comparison circuit and a counter circuit that are connected. The calculation-comparison circuit is configured to: calculate an accumulation of a value of power in power consumption data and a value of current energy, and a difference between the accumulation and a preset threshold; output a flag bit, characterizing whether the difference being less than zero, to the counter circuit; set the value of current energy to be the difference in a case that the difference is not less than zero; and set the value of current energy to be the accumulation in a case that the difference is less than zero. Calculation in electric energy metering is specifically implemented, effectively improving electric energy metering efficiency and product economic benefit.

A microprocessor for metering electric energy, a microcontroller unit thereof, and a circuit and a method for metering energy accumulation. The circuit for metering energy accumulation includes a calculation-comparison circuit and a counter circuit that are connected. The calculation-comparison circuit is configured to: calculate an accumulation of a value of power in power consumption data and a value of current energy, and a difference between the accumulation and a preset threshold; output a flag bit, characterizing whether the difference being less than zero, to the counter circuit; set the value of current energy to be the difference in a case that the difference is not less than zero; and set the value of current energy to be the accumulation in a case that the difference is less than zero. Calculation in electric energy metering is specifically implemented, effectively improving electric energy metering efficiency and product economic benefit.

A microprocessor for metering electric energy, a microcontroller unit thereof, and a circuit and a method for metering energy accumulation. The circuit for metering energy accumulation includes a calculation-comparison circuit and a counter circuit that are connected. The calculation-comparison circuit is configured to: calculate an accumulation of a value of power in power consumption data and a value of current energy, and a difference between the accumulation and a preset threshold; output a flag bit, characterizing whether the difference being less than zero, to the counter circuit; set the value of current energy to be the difference in a case that the difference is not less than zero; and set the value of current energy to be the accumulation in a case that the difference is less than zero. Calculation in electric energy metering is specifically implemented, effectively improving electric energy metering efficiency and product economic benefit.

A microprocessor for metering electric energy, a microcontroller unit thereof, and a circuit and a method for metering energy accumulation. The circuit for metering energy accumulation includes a calculation-comparison circuit and a counter circuit that are connected. The calculation-comparison circuit is configured to: calculate an accumulation of a value of power in power consumption data and a value of current energy, and a difference between the accumulation and a preset threshold; output a flag bit, characterizing whether the difference being less than zero, to the counter circuit; set the value of current energy to be the difference in a case that the difference is not less than zero; and set the value of current energy to be the accumulation in a case that the difference is less than zero. Calculation in electric energy metering is specifically implemented, effectively improving electric energy metering efficiency and product economic benefit.

A processor-implemented data processing method includes: normalizing input data of an activation function comprising a division operation; determining dividend data corresponding to a dividend of the division operation by reading, from a memory, a value of a first lookup table addressed by the normalized input data; determining divisor data corresponding to a divisor of the division operation by accumulating the dividend data; and determining output data of the activation function corresponding to an output of the division operation obtained by reading, from the memory, a value of a second lookup table addressed by the dividend data and the divisor data.

An arithmetic device includes a multiplying-accumulating (MAC) operator and an activation function (AF) circuit. The MAC operator performs a MAC arithmetic operation for weight data and vector data to generate an arithmetic result signal. The AF circuit extracts a first bit group and a second bit group from the arithmetic result signal. In addition, the AF circuit generates an input distribution signal based on the first bit group and the second bit group. Moreover, the AF circuit selects and outputs an output distribution signal that corresponds to the input distribution signal based on an activation function.