Sexagesimal-native electronic architecture and methods are provided including a sexagesimal-native semiconductor unit natively performing operations and flows using a numeral system having sixty as its base. The semiconductor unit may be an integrated circuit, an arithmetic logic unit, a central processing unit, a microcontroller, or a microchip. The sexagesimal-native semiconductor unit is configured to communicate with semiconductor units that perform operations and flows using decimal and/or binary number systems. A sexagesimal numeral method provides a sexagesimal-native arithmetic operation unit performing mathematical operations using a numeral system having sixty as its base wherein all numbers are natively processed and represented as sexagesimal numbers. A sexagesimal-native integrated circuit performs operations using a Base 60 numeral system and is configured to communicate with integrated circuits that perform operations using decimal and/or binary number systems also is provided. In exemplary sexagesimal-native electronic architecture, the chip can work with other similar chips in parallel processing mode.

Sexagesimal-native electronic architecture and methods are provided including a sexagesimal-native semiconductor unit natively performing operations and flows using a numeral system having sixty as its base. The semiconductor unit may be an integrated circuit, an arithmetic logic unit, a central processing unit, a microcontroller, or a microchip. The sexagesimal-native semiconductor unit is configured to communicate with semiconductor units that perform operations and flows using decimal and/or binary number systems. A sexagesimal numeral method provides a sexagesimal-native arithmetic operation unit performing mathematical operations using a numeral system having sixty as its base wherein all numbers are natively processed and represented as sexagesimal numbers. A sexagesimal-native integrated circuit performs operations using a Base 60 numeral system and is configured to communicate with integrated circuits that perform operations using decimal and/or binary number systems also is provided. In exemplary sexagesimal-native electronic architecture, the chip can work with other similar chips in parallel processing mode.

A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

A system for analog computing, an analog computing system with sub-binary radix weight representation is provided. The analog computing system comprises an input node, a multiplexer (MUX), a digital to analog converter (DAC), a SRAM-based Sub-Binary Multiplier (SSBM), an analog to digital converter (ADC), a switch, an output node and a calibration module. The calibration module is configured to control the analog computing system to switch between a calibration mode and a normal operation mode. Prior to being switched to the normal operation mode, the analog computing system is configured to perform a process to calibrate a weight parameter stored in the SSBM. The ADC comprises a plurality of multipliers associated with a plurality of sub-binary weight radixes. The weight parameter stored in the SSBM and the plurality of sub-binary weight radixes are configured to represent a plurality of weights for the analog computing system.

A system and method for performing discrete frequency transform including a pair of single-bit analog to digital converters (ADCs), a phase converter, a memory, a discrete frequency transform converter and summation circuitry. The ADCs convert an analog input signal into N pairs of binary in-phase and quadrature component samples each being one of four values at a corresponding one of four phases. The phase converter determines a phase value for each pair of component samples. The memory stores a set of discrete frequency transform coefficient values based on N. The discrete frequency transform converter uses a phase value and a pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin to determine a discrete frequency component for each pair of phase component samples. The summation circuitry sums the corresponding N frequency domain components for determining a frequency domain value for the selected frequency bin.

A system and method for performing discrete frequency transform including a pair of single-bit analog to digital converters (ADCs), a phase converter, a memory, a discrete frequency transform converter and summation circuitry. The ADCs convert an analog input signal into N pairs of binary in-phase and quadrature component samples each being one of four values at a corresponding one of four phases. The phase converter determines a phase value for each pair of component samples. The memory stores a set of discrete frequency transform coefficient values based on N. The discrete frequency transform converter uses a phase value and a pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin to determine a discrete frequency component for each pair of phase component samples. The summation circuitry sums the corresponding N frequency domain components for determining a frequency domain value for the selected frequency bin.

Validating microprocessor instruction execution by receiving a floating-point exception selection, receiving a validation method selection, generating validation data according to the floating-point exception selection and the validation method selection by randomly generating a first tensor element value and randomly generating a second tensor element value according to the first tensor element value and the floating-point exception selection, and executing a floating-point computation according to the validation data.

A method for deep neural network compression is provided. The method includes: using at least one weight of a deep neural network (DNN), setting a value of a P parameter, and combining every P weights in groups, and perform branch pruning and retraining, so that only one of each group has a non-zero weight, and the remaining weights are 0, wherein the remaining weights are evenly divided into branches to adjust a compression rate of the DNN and to adjust a reduction rate of the DNN.

A feedback apparatus and an FFT/IFFT processor. The apparatus comprises a radix-4 cascading operation module; radix-4 cascading operation module comprises: a twiddle factor generating unit, a complex multiplier, a delay switching unit, a butterfly operation unit, and an output switching unit; delay switching unit connects to the butterfly operation unit, complex multiplier, and output switching unit, respectively; and output switching unit connects to butterfly operation unit and delay switching unit. In present invention, on basis of the complex multiplier being fully utilized, and by using a dual-delay feedback structure circuit and designing a data delay buffer channel, the use efficiency of complex adders/subtractors is more effectively improved, the number of complex adders/subtractors required is evidently reduced, and circuit efficiency is significantly improved, thus effectively solving the problem in which radix-4SDF and radix-4SDC structures occupy a relatively large number of complex adders/subtractors.