Compute-in memory (CIM) devices are provided. A memory is configured to multiply input data by a weight to obtain an adder input. An addition circuit is configured to receive the adder input to provide an adder output, and includes a pre-computation circuit and an adder tree. The pre-computation circuit includes a parameter extractor and a parameter identification circuit. The parameter extractor is configured to extract an input parameter from the adder input. The parameter identification circuit is configured to provide a pre-computation result corresponding to the input parameter as the adder output when determining that the input parameter is present in a parameter table, and provide a control signal when determining that the input parameter is not present in the parameter table. The adder tree is configured to provide the adder output according to the adder input in response to the control signal.

Compute-in memory (CIM) devices are provided. A memory is configured to multiply input data by a weight to obtain an adder input. An addition circuit is configured to receive the adder input to provide an adder output, and includes a pre-computation circuit and an adder tree. The pre-computation circuit includes a parameter extractor and a parameter identification circuit. The parameter extractor is configured to extract an input parameter from the adder input. The parameter identification circuit is configured to provide a pre-computation result corresponding to the input parameter as the adder output when determining that the input parameter is present in a parameter table, and provide a control signal when determining that the input parameter is not present in the parameter table. The adder tree is configured to provide the adder output according to the adder input in response to the control signal.

A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

The invention is notably directed to a computing system configured to perform linear algebraic operations. The computing system comprises a co-processing module comprising a co-processing unit. The co-processing unit comprises a parallel array of bit-serial processing units. The bit-serial processing units are adapted to perform the linear algebraic operations with variable precision. The invention further concerns a related computer implemented method and a related computer program product.

The invention is notably directed to a computing system configured to perform linear algebraic operations. The computing system comprises a co-processing module comprising a co-processing unit. The co-processing unit comprises a parallel array of bit-serial processing units. The bit-serial processing units are adapted to perform the linear algebraic operations with variable precision. The invention further concerns a related computer implemented method and a related computer program product.

Cryptographic circuitry, in operation, performs a calculation on a first number and a second number. The performing of the calculation is protected by breaking the second number into a plurality of third numbers, a sum of values of the third numbers being equal to a value of the second number. The calculation is performed bit by bit for each rank of the third numbers. Functional circuitry, coupled to the cryptographic circuitry, uses a result of the calculation.

Cryptographic circuitry, in operation, performs a calculation on a first number and a second number. The performing of the calculation is protected by breaking the second number into a plurality of third numbers, a sum of values of the third numbers being equal to a value of the second number. The calculation is performed bit by bit for each rank of the third numbers. Functional circuitry, coupled to the cryptographic circuitry, uses a result of the calculation.

A method of processing an add operation in a processing apparatus includes acquiring sub-operands from input operands each having an n-bit precision, acquiring intermediate addition results by performing add operations of sub-operands in parallel by using adders, bit-shifting each of the intermediate addition results such that the intermediate addition results correspond to original bit positions in the input operands, and outputting a final addition result of the add operations of the input operands based on the bit-shifted intermediate addition results.

An example system includes a processor. The system also includes a peripheral interface that includes a controller communicatively coupled to the processor. The controller is to request information from a plurality of devices connected to the peripheral interface prior to the processor requesting the information. The controller is to provide the information to the processor.

An example system includes a processor. The system also includes a peripheral interface that includes a controller communicatively coupled to the processor. The controller is to request information from a plurality of devices connected to the peripheral interface prior to the processor requesting the information. The controller is to provide the information to the processor.