Patent classifications
G06F7/584
APPARATUSES AND METHODS FOR COUNTERING MEMORY ATTACKS
Aggressor rows may be detected by comparing access count values of word lines to a threshold value. Based on the comparison, a word line may be determined to be an aggressor row. The threshold value may be dynamically generated, such as a random number generated by a random number generator. In some examples, a random number may be generated each time an activation command is received. Responsive to detecting an aggressor row, a targeted refresh operation may be performed.
PARTICLE FILTERING AND NAVIGATION SYSTEM USING MEASUREMENT CORRELATION
Disclosed is a box-regularized particle filtering process which includes an Epanechnikov kernel smoothing step. For this purpose, the process uses a special method for generating random numbers that follow an Epanechnikov probability density function. The process can be performed autonomously in a navigation system using correlation measurement, in particular on board an aircraft such as an aircraft, a flying drone or any self-propelled aerial carrier.
RANDOM NUMBER GENERATION APPARATUS, RANDOM NUMBER GENERATION METHOD AND PROGRAM
A random number acquiring unit 15 obtains a first sequence that comprises values of digits of a random number represented by a binary number as elements. A logical product arithmetic unit 16 obtains a third sequence that is results of elementwise logical product operation between the first sequence and a second sequence that comprises values of digits of one or more Mersenne numbers represented by one or more binary numbers and a zero value as elements.
STOCHASTIC ROUNDING FOR NEURAL PROCESSOR CIRCUIT
Embodiments relate to a neural processor circuit that includes a neural engine and a post-processing circuit. The neural engine performs a computational task related to a neural network to generate a processed value. The post-processing circuit includes a random bit generator, an adder circuit and a rounding circuit. The random bit generator generates a random string of bits. The adder circuit adds the random string of bits to a version of the processed value to generate an added value. The rounding circuit truncates the added value to generate an output value of the computational task. The random bit generator may include a linear-feedback shift register (LFSR) that generates random numbers based on a seed. The seed may be derived from a master seed that is specific to a task of the neural network.
On-device bitstream validation
A programmable logic device verifies that configuration data permissibly programs the programmable logic device. The programmable logic device includes a programmable fabric having partitions to be programmed by the configuration data, a secure device manager that may generate masks based on the configuration data, and a local sector manager. The masks determine that the configuration data is configured to permissibly program the permitted partitions or that the permitted partitions have been permissibly programmed. The local sector manager applies the masks to generate an interleaved result, compares the interleaved result to an expected result, and sends an indication that the configuration data is configured to permissibly program the permitted partitions or permissibly programmed the permitted partitions in response to determining that the interleaved result is the expected result, or sends an alert to stop programming in response to determining that the interleaved result is not the expected result.
Non-linear feedback shift register
Provided are a method and system for using a non-linear feedback shift register (NLFSR) for generating a pseudo-random sequence. The method may include generating, for an n-stage NLFSR that requires more than two taps to generate a maximal length pseudo-random sequence, a pseudo-random sequence using a feedback logical operation of only a first logic gate and a second logic gate. Two non-end taps suitable for providing an at least near-maximal length pseudo-random sequence are inputs for the first logic gate, an output of the first logic gate and an end tap are inputs for the second logic gate, and an output of the second logic gate is used as feedback to a first stage of the n-stage NLFSR.
Autonomous pseudo-random seed generator for computing devices
Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate and/or support one or more operations and/or techniques for an autonomous pseudo-random seed generator (APRSG) for embedded computing devices, which may include IoT-type devices, such as implemented in connection with one or more computing and/or communication networks and/or protocols.
Semiconductor device and semiconductor storage device
A semiconductor device of an embodiment includes a seed generator circuit configured to generate a seed from inputted data by using first random number sequence data generated by an XorShift circuit; and a random number generator circuit configured to receive the seed as input to generate second random number sequence data by a second XorShift circuit.
Modular uncertainty random value generator and method
A system and method of generating a one-way function and thereby producing a random-value stream. Steps include: providing a plurality of memory cells addressed according to a domain value wherein any given domain value maps to all possible range values; generating a random domain value associated with one of the memory cells; reading a data value associated with the generated random domain value; generating dynamically enhanced data by providing an additional quantity of data; removing suspected non-random portions thereby creating source data; validating the source data according to a minimum randomness requirement, thereby creating a validated source data; and integrating the validated source data with the memory cell locations using a random edit process that is a masking, a displacement-in-time, a chaos engine, an XOR, an overwrite, an expand, a remove, a control plane, or an address plane module. The expand module inserts a noise chunk.
Echo detection of Man-in-the-Middle LAN attacks
Systems and methods are provided for detecting anomalous messages on a multipoint serial communications bus by extracting features from a first and a second message, including a time delay between the first and the second messages and, for each message, a sender address, a recipient address, a bus number, and a word count. A message transition pattern including the extracted features is generated. A probability of occurrence of the message transition pattern is determined by comparing the message transition pattern to a pattern dictionary, and the second message is determined to be anomalous when the probability is less than a predetermined threshold.