Systems and/or methods can include a ring based inverter chain that constructs multi-bit flip-flops that store time. The time flip-flops serve as storage units and enable pipeline operations. Single cells used in time series analysis, such as dynamic time warping are rendered by the time-domain circuits. The circuits include time flip-flops, Min, and ABS circuits. A and the matrix can be constructed through the single cells.

Systems and/or methods can include a ring based inverter chain that constructs multi-bit flip-flops that store time. The time flip-flops serve as storage units and enable pipeline operations. Single cells used in time series analysis, such as dynamic time warping are rendered by the time-domain circuits. The circuits include time flip-flops, Min, and ABS circuits. A and the matrix can be constructed through the single cells.

A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.

A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.

Various examples of devices, methods and systems related to pulse based arithmetic units. In one example, a pulse domain device includes an augend area calculator to provide an augend area output for an augend pulse train; an addend area calculator to provide an addend area output for an addend pulse train; a resultant sum area (RSA) decoder to provide a RSA output using the augend and addend area outputs; and a pulse timing calculator to provide RSA output pulse timing. In another example, a pulse domain device includes a multiplicand area calculator to provide an multiplicand area output for a multiplicand pulse train; a multiplier area calculator to provide a multiplier area output for a multiplier pulse train; a resultant product area (RPA) decoder to provide a RPA output using the multiplicand and multiplier area outputs; and a pulse timing calculator to provide RPA output pulse timing.

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

Various examples of devices, methods and systems related to pulse based arithmetic units. In one example, a pulse domain device includes an augend area calculator to provide an augend area output for an augend pulse train; an addend area calculator to provide an addend area output for an addend pulse train; a resultant sum area (RSA) decoder to provide a RSA output using the augend and addend area outputs; and a pulse timing calculator to provide RSA output pulse timing. In another example, a pulse domain device includes a multiplicand area calculator to provide an multiplicand area output for a multiplicand pulse train; a multiplier area calculator to provide a multiplier area output for a multiplier pulse train; a resultant product area (RPA) decoder to provide a RPA output using the multiplicand and multiplier area outputs; and a pulse timing calculator to provide RPA output pulse timing.

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.