A solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus are provided that are capable of reducing memory circuits of a column reading system, so that the column reading system can achieve a reduced layout area and eventually a reduced size. A column reading circuit includes an AD converting part and a calculating part. The AD converting part is configured to analog-to-digital convert a read-out reset signal and a read-out signal of a pixel signal read to a vertical signal line into an n-bit digital pixel signal. The calculating part includes an n-bit asynchronous counter including a retention circuit with a control logic function, which is configured to obtain a difference between an n-bit read-out reset signal and an n-bit read-out signal produced by the AD conversion performed by the AD converting part.

An open/close counting device to be attached to one of a first die and a second die which constitute a die, the die being opened by relatively moving the first die and the second die, the open/close counting device counting the number of open/close times of the die. The open/close counting device includes an open/close detecting section provided so as to face a target face of the other of the first die and the second die and to detect relative displacement of the target face along a die moving direction in non-contact condition, and includes an output section to output the open/close times counted based on detection of open/close by the open/close detecting section.

An open/close counting device to be attached to one of a first die and a second die which constitute a die, the die being opened by relatively moving the first die and the second die, the open/close counting device counting the number of open/close times of the die. The open/close counting device includes an open/close detecting section provided so as to face a target face of the other of the first die and the second die and to detect relative displacement of the target face along a die moving direction in non-contact condition, and includes an output section to output the open/close times counted based on detection of open/close by the open/close detecting section.

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

An analysis method includes: executing first accumulation processing for accumulating analysis reports including an analysis item regarding an analysis target and analysis results with respect to the analysis item; executing first extraction processing for extracting the analysis item and texts representing the analysis results from each of the analysis reports accumulated; executing first identification processing for identifying analysis techniques corresponding to the texts extracted; executing generation processing for generating analysis patterns; executing second identification processing for identifying first analysis patterns; executing third identification processing for identifying other analysis patterns; executing second accumulation processing for accumulating pattern information; executing second extraction processing for extracting the analysis item and the texts from a new analysis report; and executing output processing for identifying an analysis technique.

An analysis method includes: executing first accumulation processing for accumulating analysis reports including an analysis item regarding an analysis target and analysis results with respect to the analysis item; executing first extraction processing for extracting the analysis item and texts representing the analysis results from each of the analysis reports accumulated; executing first identification processing for identifying analysis techniques corresponding to the texts extracted; executing generation processing for generating analysis patterns; executing second identification processing for identifying first analysis patterns; executing third identification processing for identifying other analysis patterns; executing second accumulation processing for accumulating pattern information; executing second extraction processing for extracting the analysis item and the texts from a new analysis report; and executing output processing for identifying an analysis technique.

An electronic circuit and a method of making the same includes a multiplier circuit configured to perform a multiplication of a first input signal with a second input signal. The first input signal is a binary input signal that includes a sequence of input bits. The electronic circuit further includes an oscillator circuit configured to receive a result signal of the multiplication from the multiplier and to provide output pulses having an output frequency which is dependent on the result signal of the multiplication and a digital counter circuit configured to count the output pulses. The digital counter circuit is configured to provide a plurality of counter bits and to select one of the plurality of counter bits for incrementation in dependence on a significance of the corresponding input bit of the sequence of input bits.