A secure joining system is a secure joining system including a plurality of secure computing apparatuses. The plurality of secure computing apparatuses include a first vector joining unit, a first permutation calculation unit, a first vector generation unit, a second vector joining unit, a first permutation application unit, a second vector generation unit, a first inverse permutation application unit, a first vector extraction unit, a second permutation application unit, a third vector generation unit, a second inverse permutation application unit, a second vector extraction unit, a modified second table generation unit, a third permutation application unit, a fourth vector generation unit, a shifting unit, a third inverse permutation application unit, a bit inversion unit, a third vector extraction unit, a modified first table generation unit, a first table joining unit, and a first table formatting unit.

Provided is a method for performing a plurality of cryptographic operations, that upon reception of a request to perform one of said cryptographic operations, prevents an execution by said processing system of said requested cryptographic operation until a predetermined waiting time (G) has elapsed, and before said predetermined waiting time has elapsed, receives one or more requests to perform another cryptographic operation, and after said predetermined waiting time (G) has elapsed, answers (S3) said requests by executing operations comprising mutualized calculations. The method determines said waiting time depending on execution times of said cryptographic operations to be performed and of said mutualized calculations.

A processing system includes a memory and a cryptographic accelerator module operatively coupled to the memory, the cryptographic accelerator module employed to implement a byte substitute operation by performing: a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence.

A system, method and computer-readable storage medium for decrypting a code c using a modified Extended Euclidean Algorithm (EEA) having an iteration loop independent of the Hamming weight of inputs to the EEA and performing a fixed number of operations regardless of the inputs to the EEA thereby protecting a cryptographic device performing the decryption from side-channel attacks.

An optimized hardware architecture and method introducing a simple arithmetic processor that allows efficient implementation of an Elliptical Curve Cryptography point doubling algorithm for Jacobian coordinates. The optimized architecture additionally reduces the required storage for intermediate values to one intermediate value.

Hardware logic arranged to perform modulo calculation with respect to a constant value b is described. The modulo calculation is based on a finite polynomial ring with polynomial coefficients in GF(2). This ring is generated using a generator polynomial which has a repeat period (or cycle length) which is a multiple of b. The hardware logic comprises an encoding block which maps an input number into a plurality of encoded values within the ring and a decoding block which maps an output number back from the ring into binary. A multiplication block which comprises a tree of multipliers (e.g. a binary tree) takes the encoded values and multiplies groups (e.g. pairs) of them together within the ring to generate intermediate values. Groups (e.g. pairs) of these intermediate values are then iteratively multiplied together within the ring until there is only one intermediate value generated which is the output number.

A processing system includes a memory and a cryptographic accelerator module operatively coupled to the memory, the cryptographic accelerator module employed to implement a byte substitute operation by performing: a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence