A k-cluster residue number system includes a processor and a memory. The processor is used to generate a modular set composed of p coprime integers, generate a dynamic range by taking a product of the p coprime integers, generate row indices for all integers in the dynamic range, generate column indices for all integers in the dynamic range, and generate a look-up table according to the row indices, the column indices and all integers in the dynamic set. The memory is used to store the look-up table. The p coprime integers include 2.

A cryptographical apparatus for converting input bit sequences, whose overflow-free arithmetic addition results in a secret, into output bit sequences whose logic XORing results in the secret. The apparatus comprises a data interface for providing a first input bit sequence and a second input bit sequence and a processing circuit configured to a) gate the first input bit sequence and the second input bit sequence to obtain a logic result indicating overflow bit positions at which both the first input bit sequence and the second input bit sequence have a value of one; and to b) change the first and/or second input bit sequence at at least one overflow bit position. The processing circuit is configured to repeatedly perform steps a) and b) by using the respectively changed input bit sequences, until the logic result indicates no further overflow bit position and the output bit sequences are obtained.

A memory device and an operation method thereof are provided. The operation method includes: encoding an input data, sending an encoded input data to at least one page buffer, and reading out the encoded input data in parallel; encoding a first part and a second part of a weight data into an encoded first part and an encoded second part of the weight data, respectively, writing the encoded first part and the encoded second part of the weight data into a plurality of memory cells of the memory device, and reading out the encoded first part and the encoded second part of the weight data in parallel; multiplying the encoded input data with the encoded first part and the encoded second part of the weight data respectively to parallel generate a plurality of partial products; and accumulating the partial products to generate an operation result.

Various embodiments include a modulo operation generator associated with a cache memory in a computer-based system. The modulo operation generator generates a first sum by performing an addition and/or a subtraction function on an input address. A first portion of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second portion of the first sum to generate a second sum. The second sum is adjusted, as needed, to be less than the divisor. The adjusted second sum forms a residue value that identifies a cache memory slice in which the input data value corresponding to the input address is stored. By generating the residue value in this manner, the cache memory efficiently distributes input data values among the slices in a cache memory even when the number of slices is not a power of two.

An electronic calculating device (100) arranged to perform obfuscated arithmetic in a commutative ring (Z.sub.M; Z.sub.n[x]/M(x)) defined by a combined modulus (M; M(x)) in a residue number system, the residue number system being defined for a series of moduli (m.sub.1, m.sub.2, . . . , m.sub.N), each modulus defining a commutative ring (Z.sub.M1; Z.sub.n[x]/m.sub.1(x)), for each modulus (m.sub.i) of the series there exists an associated base element (u.sub.i) satisfying the condition that each ring element (x.sub.j) modulo the modulus (m.sub.j) may be expressed as an integer-list ((a.sub.j, b.sub.j)) such that the ring elements equal a linear combination of powers of the base element (xj=u.sub.i.sup.aj−u.sub.i.sup.bj), wherein the powers have exponents determined by the integer-list.

Various embodiments include a modulo operation generator associated with a cache memory in a computer-based system. The modulo operation generator generates a first sum by performing an addition and/or a subtraction function on an input address. A first portion of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second portion of the first sum to generate a second sum. The second sum is adjusted, as needed, to be less than the divisor. The adjusted second sum forms a residue value that identifies a cache memory slice in which the input data value corresponding to the input address is stored. By generating the residue value in this manner, the cache memory efficiently distributes input data values among the slices in a cache memory even when the number of slices is not a power of two.

A non-modular multiplier, a method for non-modular multiplication and a computational device are provided. The non-modular multiplier includes an interface and circuitry. The interface is configured to receive n-bit integers A and B. The circuitry is configured to calculate a non-modular product (A*B) by performing a sequence of computations, and to randomize a pattern of an electrical power consumed by the multiplier when performing the sequence. The sequence includes: generating a random number w, determining moduli M1 and M2 that depend on a number R=2.sup.k, k equals a bit-length of M1 and M2, and on the random number w, and calculating a first modular product C=A*B % M1 and a second modular product D=A*B % M2, and producing and outputting the non-modular product (A*B) based on the first and second modular products.

The disclosure discloses a multiple sinusoid signal sub-Nyquist sampling method based on a multi-channel time delay sampling system. The method includes step 1: initializing; step 2: enabling multiple sinusoid signals x(t) to respectively enter N′ parallel sampling channels after the multiple sinusoid signals are divided, wherein a sampling time delay of adjacent channels is τ, and the number of sampling points of each channel is N; step 3: combining sampled data of each sampling channel to construct an autocorrelation matrix R.sub.xx, and estimating sampling signal parameters c.sub.m of each channel and a set of frequency parameters {circumflex over (f)}.sub.m by utilizing the ESPRIT method; step 4: estimating signal amplitudes α.sub.m and another set of frequency parameters f.sub.m.sup.′ through the estimated parameters c.sub.m and the sampling time delay τ of each channel by utilizing the ESPRIT method; and step S: reconstructing 2K frequency parameters {circumflex over (f)}.sub.m through the two sets of estimated minimum frequency parameters f.sub.m and f.sub.m.sup.′ by utilizing a closed-form robust Chinese remainder theorem, and screening out K correct frequency parameters {{circumflex over (f)}.sub.k}.sub.k=0.sup.K-1 through sampling rate parameters. The disclosure is configured to solve problems of frequency aliasing and image frequency aliasing occurring in real-valued multiple sinusoid signal sub-Nyquist sampling.

Various embodiments include a modulo operation generator associated with a cache memory in a computer-based system. The modulo operation generator generates a first sum by performing an addition and/or a subtraction function on an input address. A first portion of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second portion of the first sum to generate a second sum. The second sum is adjusted, as needed, to be less than the divisor. The adjusted second sum forms a residue value that identifies a cache memory slice in which the input data value corresponding to the input address is stored. By generating the residue value in this manner, the cache memory efficiently distributes input data values among the slices in a cache memory even when the number of slices is not a power of two.

A photonic processor uses light signals and a residue number system (RNS) to perform calculations. The processor sums two or more values by shifting the phase of a light signal with phase shifters and reading out the summed phase with a coherent detector. Because phase winds back every 2π radians, the photonic processor performs addition modulo 2π. A photonic processor may use the summation of phases to perform dot products and correct erroneous residues. A photonic processor may use the RNS in combination with a positional number system (PNS) to extend the numerical range of the photonic processor, which may be used to accelerate homomorphic encryption (HE)-based deep learning.