This microprocessor is configured to compute a code C.sub.1, used to detect an execution fault, using a relationship C.sub.i=P o F.sub.α(D.sub.i), where: F.sub.α(D.sub.i)=E.sub.0 o . . . o E.sub.q o . . . o E.sub.NbE−1(D.sub.i), E.sub.q(x)=T.sub.αm,q o . . . o T.sub.αj,q o . . . o T.sub.α1,q o T.sub.α0,q(X), and T.sub.αj,q is a conditional transposition, configured by a secret parameter α.sub.j,q, that permutes two blocks of bits B.sub.2j+1,q and B.sub.2j,q of the variable x only when the parameter a.sub.j,q is equal to a first value, the blocks B.sub.2j+1,q and B.sub.2j,q of all of the transpositions T.sub.αj,q of the stage E.sub.q being different from one another and not overlapping and the blocks B.sub.2j+1,q and B.sub.2j,q are placed within one and the same block of greater size permuted by a transposition of the higher stage E.sub.q+1.

Circuitry, systems, and methods are provided for an integrated circuit that includes digital filter circuitry. The digital filtering circuitry includes a first partial filter that includes a first number of taps corresponding to coefficients of a first bit depth and a second partial filter that includes a second number of taps corresponding to coefficients of a second bit depth.

A method includes loading a data element from at least one memory into at least one internal register. The method also includes converting the data element from a network standardized format to a device native format. The method further includes performing an operation on the data value. The method also includes de-converting the data element from the device native format to the network standardized format. In addition, the method includes storing the data element in the at least one memory.

To achieve authentication of devices with higher security.

A system includes: a first device, and a plurality of second devices. The first device transmits a generated confirmation request including first information to the second devices. Each of the second devices performs an arithmetic operation based on the received confirmation request, second information set in common for the second devices, and an arithmetic method specific to each of the second devices, and transmits a confirmation response including a result of the arithmetic operation to the first device. The first device authenticates each of the second devices on the basis of the confirmation response transmitted by each of the second devices.

Systems and methods for wear leveling in non-volatile memories (NVMs) are disclosed. One such system includes a cumulative control state determiner configured to determine a cumulative control state indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of an NVM, an access network configured to translate a LBA to a PBA based on the cumulative control state, and a background swap scheduler configured to swap PBAs assigned to preselected LBAs based on a control state. One such method involves determining a cumulative control state indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of an NVM, translating a LBA to a PBA based on the cumulative control state, and swapping PBAs assigned to preselected LBAs based on a control state.

Systems and methods for wear leveling in non-volatile memories (NVMs) are illustrated. One such system includes a first non-volatile memory configured to store information from a host, a second non-volatile memory storing a plurality of cumulative control states, each indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of the first non-volatile memory, and a plurality of control states, an access network configured to translate LBAs to PBAs based on the plurality of cumulative control states, a background swap scheduler configured to swap PBAs assigned to LBAs based on the plurality of control states, and a controller configured to sequentially advance through the plurality of cumulative control states and the plurality of control states.

A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.

Cryptographic methods and systems are described. Certain examples relate to performing cryptographic operations that involve a cryptographic permutation. The methods and systems may be used to provide cryptographic functions such as hashing, encryption, decryption and random number generation. In one example, a cryptographic architecture is provided. The cryptographic architecture has a processor interface comprising a set of cryptographic registers, where the processor interface is accessible by at least one processing unit. The cryptographic architecture also has a cryptographic permutation unit comprising circuitry to perform a cryptographic permutation using data stored within the set of cryptographic registers. In examples, the at least one processing unit instructs the cryptographic permutation and accesses a result of the cryptographic permutation using the processor interface.

A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.

An information processing device includes: a memory; and a processor coupled to the memory, the processor being configured to: sort stream data buffered in units of wraps of a sequential recording medium, in a column order and a time order of the stream data, as primary data to be written into a primary wrap of the sequential recording medium; and control writing of the sorted primary data into the primary wrap, wherein the sorting of the stream data is configured to sort secondary data to be written into a secondary wrap that follows the primary wrap, in a reverse order of the column order and in the time order, and wherein the controlling of the primary data is configured to control writing of the sorted secondary data into the secondary wrap.