Patent classifications
G06F7/785
Method and transfer device for transferring data blocks
A method for transferring data blocks from a field device to a server, each data block including data describing an operation of the field device during a block time period is provided. The method includes setting a first and a second pointer delimiting a completed time period; and, until a predetermined transfer period elapses: transferring the data blocks having a block time period that is later than the second pointer to the server in a chronological order; and if all data blocks having a block time period that is later than the second pointer have been transferred to the server, transferring the data blocks having a block time period that is earlier than the first pointer to the server in an anti-chronological order. Data blocks can efficiently and reliably be transferred to the server.
Transpose memory unit for multi-bit convolutional neural network based computing-in-memory applications, transpose memory array structure for multi-bit convolutional neural network based computing-in-memory applications and computing method thereof
A transpose memory unit for a plurality of multi-bit convolutional neural network based computing-in-memory applications includes a memory cell and a transpose cell. The memory cell stores a weight. The transpose cell is connected to the memory cell and receives the weight from the memory cell. The transpose cell includes an input bit line, at least one first input word line, a first output bit line, at least one second input word line and a second output bit line. One of the at least one first input word line and the at least one second input word line transmits at least one multi-bit input value, and the transpose cell is controlled by the second word line to generate a multiply-accumulate output value on one of the first output bit line and the second output bit line according to the at least one multi-bit input value multiplied by the weight.
System and method of input alignment for efficient vector operations in an artificial neural network
A novel and useful system and method of input alignment for streamlining vector operations that reduce the required memory read bandwidth. The input aligner as deployed in the NN processor, functions to facilitate the reuse of data read from memory and to avoid having to re-read that data in the context of neural network calculations. The input aligner functions to distribute input data (or weights) to the appropriate compute elements while consuming input data in a single cycle. Thus, the input aligner is operative to lower the required read bandwidth of layer input in an ANN. This reflects the fact that normally in practice, a vector multiplication is performed every time instance. This considers the fact that in many native calculations that take place in an ANN, the same data point is involved in multiple calculations.
TRANSPOSE MEMORY UNIT FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS, TRANSPOSE MEMORY ARRAY STRUCTURE FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF
A transpose memory unit for a plurality of multi-bit convolutional neural network based computing-in-memory applications includes a memory cell and a transpose cell. The memory cell stores a weight. The transpose cell is connected to the memory cell and receives the weight from the memory cell. The transpose cell includes an input bit line, at least one first input word line, a first output bit line, at least one second input word line and a second output bit line. One of the at least one first input word line and the at least one second input word line transmits at least one multi-bit input value, and the transpose cell is controlled by the second word line to generate a multiply-accumulate output value on one of the first output bit line and the second output bit line according to the at least one multi-bit input value multiplied by the weight.
METHOD AND TRANSFER DEVICE FOR TRANSFERRING DATA BLOCKS
A method for transferring data blocks from a field device to a server, each data block including data describing an operation of the field device during a block time period is provided. The method includes setting a first and a second pointer delimiting a completed time period; and, until a predetermined transfer period elapses: transferring the data blocks having a block time period that is later than the second pointer to the server in a chronological order; and if all data blocks having a block time period that is later than the second pointer have been transferred to the server, transferring the data blocks having a block time period that is earlier than the first pointer to the server in an anti-chronological order. Data blocks can efficiently and reliably be transferred to the server.
Method for dividing the data based on a persistent data queue
The invention proposes a method for dividing archived data based on persistent queue (PQ), including i) dividing this stored data into persistent data queues corresponding to the time it needs to be processed in the future; ii) scheduling the processing of data that has been split into these persistent data queues corresponding to future milestones; and iii) redistribute stored data into new sustainable data queues corresponding to the next time it takes for further processing of this data.
Memory systems including support for transposition operations and related methods and circuits
A method operating a memory system, can be provided by reading a plurality of data words from a memory system, where each of the plurality of data words is stored in the memory system in a first dimension-major order. The plurality of data words can be shifted into a transpose memory system in the first dimension in parallel with one another using first directly time adjacent clock edges to store a plurality of transposed data words in a second dimension-major order in the transpose memory system relative to the memory system. The plurality of transposed data words can be shifted out of the transpose memory system in the second dimension using second directly time adjacent clock edges.
κ-selection using parallel processing
In one embodiment, a method includes accessing a query vector; accessing object vectors; determining input distances corresponding to a distance between the query vector and the object vectors; accessing thread queues; accessing a warp queue; for each of the input distance values: selecting one of the thread queues, when the input distance value is less than a greatest one of the distance values stored in the selected thread queue, inserting the input distance value into the thread queues and ejecting the greatest distance values stored in the thread queue, and when a greatest distance value stored in any of the thread queues is less than a greatest distance value stored in the warp queue, merging the thread queue with the warp queue; identifying the objects represented by an object vector corresponding to the distance values stored in the warp queue; and providing the search results for presentation.
System And Method Of Input Alignment For Efficient Vector Operations In An Artificial Neural Network
A novel and useful system and method of input alignment for streamlining vector operations that reduce the required memory read bandwidth. The input aligner as deployed in the NN processor, functions to facilitate the reuse of data read from memory and to avoid having to re-read that data in the context of neural network calculations. The input aligner functions to distribute input data (or weights) to the appropriate compute elements while consuming input data in a single cycle. Thus, the input aligner is operative to lower the required read bandwidth of layer input in an ANN. This reflects the fact that normally in practice, a vector multiplication is performed every time instance. This considers the fact that in many native calculations that take place in an ANN, the same data point is involved in multiple calculations.
MEMORY SYSTEMS INCLUDING SUPPORT FOR TRANSPOSITION OPERATIONS AND RELATED METHODS AND CIRCUITS
A method operating a memory system, can be provided by reading a plurality of data words from a memory system, where each of the plurality of data words is stored in the memory system in a first dimension-major order. The plurality of data words can be shifted into a transpose memory system in the first dimension in parallel with one another using first directly time adjacent clock edges to store a plurality of transposed data words in a second dimension-major order in the transpose memory system relative to the memory system. The plurality of transposed data words can be shifted out of the transpose memory system in the second dimension using second directly time adjacent clock edges.