In some embodiments, a real-time event is detected and context is determined based on the real-time event. An application model is fetched based on the context and meta-data associated with the real-time event, the application model referencing a micro-function and including pre-condition and post-condition descriptors. A graph is constructed based on the micro-function. The micro-function is transformed into micro-capabilities by determining a computing resource for execution of a micro-capability by matching pre-conditions and post-conditions of the micro-capability, and enabling execution and configuration of the micro-capability on the computing resource by providing access in a target environment to an API capable of calling the micro-capability to configure and execute the micro-capability. A request is received from the target environment to execute and configure the micro-capability on the computing resource. The micro-capability is executed and configured on the computing resource, and an output of the micro-capability is provided to the target environment.

In some embodiments, a real-time event is detected and context is determined based on the real-time event. An application model is fetched based on the context and meta-data associated with the real-time event, the application model referencing a micro-function and including pre-condition and post-condition descriptors. A graph is constructed based on the micro-function. The micro-function is transformed into micro-capabilities by determining a computing resource for execution of a micro-capability by matching pre-conditions and post-conditions of the micro-capability, and enabling execution and configuration of the micro-capability on the computing resource by providing access in a target environment to an API capable of calling the micro-capability to configure and execute the micro-capability. A request is received from the target environment to execute and configure the micro-capability on the computing resource. The micro-capability is executed and configured on the computing resource, and an output of the micro-capability is provided to the target environment.

A compilation system can define, at compile time, the data blocks to be managed by an Even Driven Task (EDT) based runtime/platform, and can also guide the runtime/platform on when to create and/or destroy the data blocks, so as to improve the performance of the runtime/platform. The compilation system can also guide, at compile time, how different tasks may access the data blocks they need in a manner that can improve performance of the tasks.

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

This disclosure relates generally to the field of source code processing, and, more particularly to a method and system for identification of redundant function-level slicing calls. The method disclosed generates program dependence graphs (PDGs) based on a slicing criteria and a function corresponding to the function-level slicing call. Further the method classifies the function-level slicing call into redundant or non-redundant by traversing the PDGs and checking if a predefined condition is satisfied or not. The function-level slicing calls are classified as redundant if the check is not satisfied and are classified as non-redundant if the check is satisfied. The disclosed method can be used in identifying redundant function-level slicing calls in applications such as automated false positive elimination (AFPE), automated test case generation and so on.

A distillation system extracts knowledge from a large pre-trained sequence-to-sequence neural transformer model into a smaller bi-encoder. The pre-trained sequence-to-sequence neural transformer model is trained to translate data from a first domain into a second domain on a large corpus. A teacher model is generated from the pre-trained model by fine-tuning the pre-trained neural transformer model on a smaller translation task with true translation pairs. The fine-tuned model is then used to generate augmented data values which are used with the true translation pairs to train the bi-encoder. The bi-encoder is used for perform cross-domain searches.

A distillation system extracts knowledge from a large pre-trained sequence-to-sequence neural transformer model into a smaller bi-encoder. The pre-trained sequence-to-sequence neural transformer model is trained to translate data from a first domain into a second domain on a large corpus. A teacher model is generated from the pre-trained model by fine-tuning the pre-trained neural transformer model on a smaller translation task with true translation pairs. The fine-tuned model is then used to generate augmented data values which are used with the true translation pairs to train the bi-encoder. The bi-encoder is used for perform cross-domain searches.

Techniques are disclosed for utilizing configurable delays in an instruction stream. A set of instructions to be executed on a set of engines are generated. The set of engines are distributed between a set of hardware elements. A set of configurable delays are inserted into the set of instructions. Each of the set of configurable delays includes an adjustable delay amount that delays an execution of the set of instructions on the set of engines. The adjustable delay amount is adjustable by a runtime application that facilitates the execution of the set of instructions on the set of engines. The runtime application is configured to determine a runtime condition associated with the execution of the set of instructions on the set of engines and to adjust the set of configurable delays based on the runtime condition.

Computer software development has produced many advances within computer science and in most aspects of modern society. Even with modern quality control, bug finding, and other code checking applications, computer software is often less than ideal. A developer may write code that is functionally accurate but lacks security, documentation, speed, storage, reusability, or other element that may make a segment of software code less than ideal. Identifying equivalent code and, when found, replacing it with a vetted equivalent promotes the deployment of software that is more robust, secure, usable and reusable, and/or satisfies performance or other objectives.