Patent classifications
G06F8/654
Data storage device restoring method
A data storage device restoring method is provided, which is adapted to a data storage device. The data storage device includes an SSD controller, a power management circuit, a non-volatile memory, and a reset circuit. The data storage device restoring method includes: the power management circuit determines whether a normal signal from the SSD controller is received within a predetermined time; if not, the power management circuit resupplies power to the data storage device but stops supplying power to the non-volatile memory, thereby the SSD controller stays in a read-only memory mode to automatically execute the data storage device restoring process.
Data storage device restoring method
A data storage device restoring method is provided, which is adapted to a data storage device. The data storage device includes an SSD controller, a power management circuit, a non-volatile memory, and a reset circuit. The data storage device restoring method includes: the power management circuit determines whether a normal signal from the SSD controller is received within a predetermined time; if not, the power management circuit resupplies power to the data storage device but stops supplying power to the non-volatile memory, thereby the SSD controller stays in a read-only memory mode to automatically execute the data storage device restoring process.
Wireless earphones with hanger bars
A wireless earphone comprises a transceiver circuit for receiving streaming audio from a data source over a local ad hoc wireless network. When the data source and the earphone are out of range, they transition automatically to an infrastructure wireless network. If there is no common infrastructure wireless network for both the data source and the speakerphone set, the earphone connects to a host server via an available wireless network.
Hierarchal controller logic with incremental updates
A controller that is configured to control operation of a building component may be programmed using a programming tool to build a controller logic that utilizes sub-structures organized within a hierarchal tree, which may then be downloaded to the controller. The controller is operated via the controller logic such that the controller controls operation of the building component. The programming tool may subsequently be used to update one or more of the sub-structures. The one or more updated sub-structures may be downloaded to the controller while not downloading one or more of the sub-structures that were not updated. The method includes continuing to control operation of the building component using the controller logic that now includes the one or more updated sub-structures.
Hierarchal controller logic with incremental updates
A controller that is configured to control operation of a building component may be programmed using a programming tool to build a controller logic that utilizes sub-structures organized within a hierarchal tree, which may then be downloaded to the controller. The controller is operated via the controller logic such that the controller controls operation of the building component. The programming tool may subsequently be used to update one or more of the sub-structures. The one or more updated sub-structures may be downloaded to the controller while not downloading one or more of the sub-structures that were not updated. The method includes continuing to control operation of the building component using the controller logic that now includes the one or more updated sub-structures.
Technologies for providing shared memory for accelerator sleds
Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.
Technologies for providing shared memory for accelerator sleds
Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.
FIRMWARE MASSIVE UPDATE METHOD USING FLASH MEMORY AND COMPUTER PROGRAM STORED IN RECORDING MEDIA FOR EXECUTING THE SAME
A firmware massive update method using a flash memory includes: a firmware data registration step of receiving, from a manufacturer server, at least one of information of a user device that is a firmware update target, and firmware information and registering the received information as firmware data; a firmware data management step of receiving a request from a firmware update server in which the registered firmware data is stored, and storing and managing the registered firmware data in a specific area of a flash memory included in the user device via a network; and a firmware update execution step of executing a firmware update on the firmware data managed in the specific area of the flash memory included in the user device through the firmware update server.
FIRMWARE MASSIVE UPDATE METHOD USING FLASH MEMORY AND COMPUTER PROGRAM STORED IN RECORDING MEDIA FOR EXECUTING THE SAME
A firmware massive update method using a flash memory includes: a firmware data registration step of receiving, from a manufacturer server, at least one of information of a user device that is a firmware update target, and firmware information and registering the received information as firmware data; a firmware data management step of receiving a request from a firmware update server in which the registered firmware data is stored, and storing and managing the registered firmware data in a specific area of a flash memory included in the user device via a network; and a firmware update execution step of executing a firmware update on the firmware data managed in the specific area of the flash memory included in the user device through the firmware update server.
Program update management device
Provided is a program update management device that includes: an acquiring part that acquires a scene signal indicating a scene in which a vehicle is used; a determining part that determines a level indicating how strongly the vehicle is restricted when respective functions of a plurality of ECUs are impaired, the plurality of ECUs each having the same function in the scene indicated by the scene signal; and a selecting part that selects, from among the plurality of ECUs, an ECU for which a program update is performed, based on the level.