Patent classifications
G06F9/226
Analytic workload partitioning for security and performance optimization
The present disclosure provides privacy preservation of analytic workflows based on splitting the workflow into sub-workflows each with different privacy-preserving characteristics. Libraries are generated that provide for formatting and/or encrypting data for use in the sub-workflows and also for compiling a machine learning algorithm for the sub-workflows. Subsequently, the sub-workflows can be executed using the compiled algorithm and formatted data.
Pipelined micro controller unit
A 3D NAND memory device is provided in which control is performed by two microcontroller units (MCU). During manufacture of the memory device, bug fixes required for the controller may be addressed using a software solution by which an instruction requiring correction in one of the two MCUs is replaced with a corrected instruction stored in a RAM.
MULTIMEDIA CONTENT EDITING CONTROLLER AND CONTROL METHOD THEREOF
A multimedia content editing controller includes a microcontroller, a data storage device, a display device and a function selection device. The microcontroller receives plural editing function options from an external computer host. The plural editing function options are stored in the data storage device. The plural editing function options are displayed on the display device. When a user performs at least one function selection operation through the function selection device, the microcontroller determines at least one selected editing function option from the plural editing function options, and the microcontroller generates a human-machine interaction control signal. The at least one selected editing function option is transmitted from the microcontroller to the external computer host. The human-machine interaction control signal is transmitted to at least one of the display device and a LED display module.
ENSURING FUNCTIONAL SAFETY REQUIREMENT SATISFACTION USING FAULT-DETECTABLE MICROCONTROLLER IDENTIFIERS
An application processor receives first and safety state information from first and second microcontrollers, and respective first and second sets of bytes forming a first identifier of the first microcontroller and a second identifier of the second microcontroller. The processor concatenates a safety message including the first and second safety state information, the safety message including the first set of bytes and the second set of bytes. The processor transmits the safety message to a second application processor of a safety controller, which separates, the first set of bytes and the second set of bytes, compares at least one of the first set of bytes and the second set of bytes to a data structure of known microcontroller identifiers, and verifies the safety state information based on identifying a match.
Dynamic re-evaluation of parameters for non-volatile memory using microcontroller
A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.
Machine learning model for micro-service compliance requirements
Embodiments relate to a computer system, computer program product, and computer-implemented method to train a machine learning (ML) model using artificial intelligence to learn an association between (regulatory) compliance requirements and features of micro-service training datasets. The trained ML model is leveraged to determine the compliance requirements of a micro-service requiring classification. In an exemplary embodiment, once the micro-service has been classified with respect to applicable compliance requirements, the classified micro-service may be used as an additional micro-service training dataset to further train the ML model and thereby improve its performance.
Noisy instructions for side-channel attack mitigation
Described herein are systems and methods using noisy instructions for side-channel attack mitigation. For example, some methods include fetching an instruction from a memory into a processor pipeline of a processor core that is configured to execute instructions using an architectural state of the processor core; generating a random number; fissioning the instruction into a set of micro-operations that includes one or more micro-operations that perform the instruction and the random number of noisy micro-operations, wherein each of the noisy micro-operations does not affect the architectural state; executing the set of micro-operations using one or more execution units of the processor pipeline; and, retiring, responsive to completion of execution of the set of micro-operations, the instruction.
Micro-application creation and execution
A method for creating and executing a micro-application includes receiving a user selection of a user interface element within a user interface of a primary application. Source code associated with the selected user interface element is parsed to obtain at least one attribute associated with the selected user interface element. Data associated with the selected user interface element is identified based on the source code. A response based on the at least one attribute and the data is generated. A microapp configured to process the response to obtain the data from within the primary application is generated.
Error recovery for intra-core lockstep mode
An apparatus has a processing pipeline (2) comprising an execute stage (30) and at least one front end stage (10), (20), (25) for controlling which micro operations are issued to the execute stage. The pipeline has an intra-core lockstep mode of operation in which the at least one front end stage (10), (20), (25) issues micro operations for controlling the execute stage (30) to perform main processing and checker processing. The checker processing comprises redundant operations corresponding to associated main operations of at least part of the main processing. Error handling circuitry (200), (210) is responsive to the detection of a mismatch between information associated with given checker and main operations to trigger a recovery operation to correct an error and continue forward progress of the main processing.
VARYING FIRMWARE FOR VIRTUALIZED DEVICE
A technique for varying firmware for different virtual functions in a virtualized device is provided. The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a “time-slice” during which work is performed for that function. To vary the firmware, each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function. The addresses for the firmware are provided by a corresponding virtual machine at configuration time.