G06F9/3891

Correspondence of external operations to containers and mutation events

A method is provided for determining command-to-process correspondence. The method includes identifying, by the hardware processor, initial processes resulting from executions of container immutability change events for each of multiple containers in a cluster, based on an execution time, a process identifier and a process group identifier for each of the container immutability change events. The method further includes checking, by the hardware processor, if an initial process from among the identified initial processes matches an entry in a database that stores external container commands and at least one respective process resulting from executing each of the external container commands. The method also includes designating, by the hardware processor, a particular external command, from among the external container commands stored in the database, as having a correspondence to the initial process, responsive to the initial process matching the at least one respective process resulting from executing the particular external command.

Scheduler for amp architecture with closed loop performance and thermal controller

Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

Distributed processing architecture

Embodiments of the present disclosure include techniques for processing neural networks. Various forms of parallelism may be implemented using topology that combines sequences of processors. In one embodiment, the present disclosure includes a computer system comprising a plurality of processor groups, the processor groups each comprising a plurality of processors. A plurality of network switches are coupled to subsets of the plurality of processor groups. A subset of the processors in the processor groups may be configurable to form sequences, and the network switches are configurable to form at least one sequence across one or more of the plurality of processor groups to perform neural network computations. Various alternative configurations for creating Hamiltonian cycles are disclosed to support data parallelism, pipeline parallelism, layer parallelism, or combinations thereof.

Big data application lifecycle management

Aspects of the present disclosure involve systems, methods, devices, and the like for creating an application lifecycle management platform for big data applications. In one embodiment the lifecycle management platform can include a multiple-layer container file that integrates multiple big-data tools/platforms. The system may create a generic template application, create a build environment for the generic template application, create a test environment for the generic template application, and run the built generic template application in the test environment prior to the user writing any new code in the generic template application. In one embodiment, the test environment includes a container management system or virtual machine that launches the big data application (which may be the generic template application before a developer edits the file) on a separate big-data server cluster.

Technologies for providing shared memory for accelerator sleds

Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.

Transaction-enabled systems and methods for royalty apportionment and stacking

Transaction-enabled systems and methods for royalty apportionment and stacking are disclosed. An example system may include a plurality of royalty generating elements (a royalty stack) each related to a corresponding one or more of a plurality of intellectual property (IP) assets (an aggregate stack of IP). The system may further include a royalty apportionment wrapper to interpret IP licensing terms and apportion royalties to a plurality of owning entities corresponding to the aggregate stack of IP in response to the IP licensing terms and a smart contract wrapper. The smart contract wrapper is configured to access a distributed ledger, interpret an IP description value and IP addition request, to add an IP asset to the aggregate stack of IP, and to adjust the royalty stack.

Traversing a large connected component on a distributed file-based data structure

A distributed system including multiple processing nodes. The distributed system can perform certain acts. The acts can include receiving a set of input nodes and a set of criteria. The acts can include obtaining an adjacency list representing a large connected component. The large connected component can include nodes, edges, and edge metadata. A quantity of the nodes of the large connected component can exceed 1 billion. The adjacency list can be distributed across the multiple processing nodes. The nodes of the large connected component can include the input nodes. The acts also can include performing one or more iterations of traversing the large connected component until a stopping condition is satisfied. Each iteration can include processing a set of input nodes at the multiple processing nodes using the set of criteria to generate first data at the multiple processing nodes, determining a set of output nodes such that each output node of the set of output nodes is one hop from a respective input node of the set of input nodes, consolidating the first data from the multiple processing nodes to a first processing node of the multiple processing nodes, processing the first data at the first processing node; and assigning the set of input nodes for a subsequent iteration of the one or more iterations based on the set of output nodes when the stopping condition is not satisfied. The acts further can include outputting second data based on the first data received and processed at the first processing node during the one or more iterations. Other embodiments are disclosed.

Method for selectively deploying sensors within an agricultural facility

One variation of a method for deploying sensors within an agricultural facility includes: accessing scan data of a set of modules deployed within the agricultural facility; extracting characteristics of plants occupying the set of modules from the scan data; selecting a first subset of target modules from the set of modules, each target module in the set of target modules containing a group of plants exhibiting characteristics representative of plants occupying modules neighboring the target module; for each target module, scheduling a robotic manipulator within the agricultural facility to remove a particular plant from a particular plant slot in the target module and load the particular plant slot with a sensor pod from a population of sensor pods deployed in the agricultural facility; and monitoring environmental conditions at target modules in the first subset of target modules based on sensor data recorded by the first population of sensor pods.

Transaction-enabling systems and methods for customer notification regarding facility provisioning and allocation of resources

The present disclosure describes transaction-enabling systems and methods. A system can include a facility including a core task including a customer relevant output and a controller. The controller may include a facility description circuit to interpret a plurality of historical facility parameter values and corresponding facility outcome values and a facility prediction circuit to operate an adaptive learning system, wherein the adaptive learning system is configured to train a facility production predictor in response to the historical facility parameter values and the corresponding outcome values. The facility description circuit also interprets a plurality of present state facility parameter values, wherein the trained facility production predictor determines a customer contact indicator in response to the plurality of present state facility parameter values and a customer notification circuit provides a notification to a customer in response.

COMPUTING DEVICE WITH ONE OR MORE HARDWARE ACCELERATORS DIRECTLY COUPLED WITH CLUSTER OF PROCESSORS
20230037780 · 2023-02-09 ·

A computing device having a tightly attached or closely attached hardware accelerator directly coupled with one or more processors for efficient uses of the hardware accelerator for executing specific functions are described. According to an embodiment, the hardware accelerator is instantiated inside the main processor unit and interfaces to a load-store unit (LS) using virtual addresses. The hardware accelerator instantiated inside the main processing unit (e.g., core) is referred to as a tightly attached hardware accelerator. In an alternative embodiment, the hardware accelerator is instantiated inside a cluster of processor cores. The hardware accelerator that is instantiated inside the cluster of processor cores but not inside a specific processor core is referred to as a closely attached hardware accelerator.