A secondary processor device ownership assignment system includes a chassis that houses devices, a secondary processing system, a central processing system that includes an integrated switch device that is coupled to each of the devices and the secondary processing system, and a device ownership subsystem that is coupled to the central processing system. The device ownership system accesses device information for a subset of the devices that will be owned by the secondary processing system, and configures the device information for the subset of the devices such that the subset of the devices are hidden from an operating system provided by the central processing system. The secondary processing system reconfigures the device information for the subset of the plurality of devices such that the subset of the plurality of devices are accessible by the secondary processing system.

An autonomous driving controller includes a plurality of parallel processors operating on common input data. Each of the plurality of parallel processors includes a general processor, a security processor subsystem (SCS), and a safety subsystem (SMS). The general processors, the SCSs, and the SMSs of the plurality of parallel processors are configured to first, boot the plurality of SCSs from ROM second, boot the plurality of SMSs of the plurality of parallel processors from RAM or ROM, and, third, boot the plurality of general processors of the plurality of parallel processors from RAM. Between booting of the SCSs and the SMSs, at least one of the plurality of SCSs may load SMS boot code into the RAM that is dedicated to the plurality of SMSs.

Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

A multi-phase boot operation of a virtualization manager at a virtualization host is initiated at an offload card. In a first phase of the boot, a security key stored in a tamper-resistant location of the offload card is used. In a second phase, firmware programs are measured using a security module, and a first version of a virtualization coordinator is instantiated at the offload card. The first version of the virtualization coordinator obtains a different version of the virtualization coordinator and launches the different version at the offload card. Other components of the virtualization manager (such as various hypervisor components that do not run at the offload card) are launched by the different version of the virtualization controller.

A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.

A node that includes data processing unit (DPU) and a processor, where the processor is configured to perform a method for utilizing a data processing unit (DPU), that includes identifying, by the DPU, a processing entity operatively connected to the DPU, receiving processing entity properties from the processing entity, storing the processing entity properties in a processing entity catalog, generating a virtual combined memory space in the processing entity catalog, and providing access to the processing entity catalog to a BIOS.

A system-on-chip (SoC) for operating a plurality of different central processing units and a method for operating the same are provided. The SoC includes a plurality of central processing units (CPUs) that execute respective software programs independently of each other, a bus interconnector for connecting the plurality of CPUs, and at least one access control device that is connected to the bus interconnector and controls each access to a physical resource shared by the plurality of CPUs via the bus interconnector, for each CPU.

In various examples there is a computing device comprising: a first microcontroller comprising a first immutable bootloader and first mutable firmware. The first immutable bootloader uses a unique device secret burnt into hardware of the computing device in order to generate an attestation of the first mutable firmware. The computing device has a second microcontroller. There is second mutable firmware at the second microcontroller. There is a second immutable bootloader at the second microcontroller which sends a measurement of the second mutable firmware to the first immutable bootloader whenever the second microcontroller restarts, such that the first microcontroller is able to include the measurement in the attestation.

An electronic device is provided. The electronic device includes a first power management integrated circuit (PMIC) with a first fault controller connected to a first node and a first interface circuit connected to a second node; a second PMIC with a second fault controller connected to the first node and a second interface circuit connected to the second node; and a third PMIC with a third fault controller connected to the first node and a third interface circuit connected to the second node. The first fault controller is configured to, during a power on sequence or a power off sequence, detect a change in a voltage level of the first node. The first interface circuit is configured to communicate with any one or any combination of the second interface circuit and communication and the third interface circuit based on the change in the voltage level of the first node.

Software configuration deployment techniques for disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes presenting a user interface configured to receive instructions related to deployment of software to compute units, and receiving user selections of a software element for deployment to a compute unit comprising a processing element and a storage element. Responsive to the user selections, the method includes instructing a management processor of a communication fabric to deploy the software element for use by the compute unit by at least establishing a first partitioning in the communication fabric between the management processor and the storage element, deploying the software element to the storage element using the first partitioning, de-establishing the first partitioning, and establishing a second partitioning in the communication fabric between the processing element and the storage element comprising the software element, wherein the processing element operates using the software element.