An architecture for a load-balanced groups of multi-stage manycore processors shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing.

The method comprises: connecting to a plurality of AI computing boards in an AI processing resource pool and a plurality of video encoding and decoding boards in a video processing resource pool by means of a unified high-speed interface; respectively allocating a specified number of AI computing boards and video encoding and decoding boards on account of resources and bandwidths required for completing a processing task to form a temporary cooperation relationship based on the processing task; in response to resource overflow or insufficiency in the AI processing resource pool or the video processing resource pool caused by a processing task change, accessing more AI computing boards or video encoding and decoding boards or stopping using redundant AI computing boards or video encoding and decoding boards; performing the processing task on account of the allocated AI computing boards or video encoding and decoding boards, and releasing the temporary cooperation relationship.

Disclosed embodiments relate to software control of graphics hardware that supports logical slots. In some embodiments, a GPU includes circuitry that implements a plurality of logical slots and a set of graphics processor sub-units that each implement multiple distributed hardware slots. Control circuitry may determine mappings between logical slots and distributed hardware slots for different sets of graphics work. Various mapping aspects may be software-controlled. For example, software may specify one or more of the following: priority information for a set of graphics work, to retain the mapping after completion of the work, a distribution rule, a target group of sub-units, a sub-unit mask, a scheduling policy, to reclaim hardware slots from another logical slot, etc. Software may also query status of the work.

Disclosed embodiments relate to controlling sets of graphics work (e.g., kicks) assigned to graphics processor circuitry. In some embodiments, tracking slot circuitry implements entries for multiple tracking slots. Slot manager circuitry may store, using an entry of the tracking slot circuitry, software-specified information for a set of graphics work, where the information includes: type of work, dependencies on other sets of graphics work, and location of data for the set of graphics work. The slot manager circuitry may prefetch, from the location and prior to allocating shader core resources for the set of graphics work, configuration register data for the set of graphics work. Control circuitry may program configuration registers for the set of graphics work using the prefetched data and initiate processing of the set of graphics work by the graphics processor circuitry according to the dependencies. Disclosed techniques may reduce kick-to-kick transition time, in some embodiments.

A master electronic apparatus, an electronic apparatus, and a controlling method thereof where the master electronic apparatus includes a communication interface and a processor. The processor receives first data and second data regarding predicted power consumption amounts corresponding to respective tasks of a first electronic apparatus and a second electronic apparatus, calculates summed-up values of the predicted power consumption amounts for respective times, and compares the summed-up values with instantaneous power amount limits for the respective times. The processor, based on the summed-up values being smaller than the instantaneous power amount limits, transmits a task approval signal to the second electronic apparatus, and based on identifying a time a summed-up value is greater than or equal to the instantaneous power amount limit, transmits a control signal controlling an operation in the identified time to at least one of the first electronic apparatus and the second electronic apparatus based on priorities.

A method, computer program and apparatus is disclosed. The method, performed by one or more processors, may comprise receiving, from one or more predetermined organizations, datasets representing entities and datasets representing one or more tasks for those entities and storing in a database, in accordance with an ontology which is common to the organizations, the received one or more datasets as data objects, the ontology defining properties of data objects and relationships between the data objects. The method may also comprise mapping the data objects stored in the database to the organization from which the one or more datasets were received and receiving, through a querying application, a query from a user of one of the predetermined organizations to view one or more data objects relating to a task. The method may also comprise identifying the organization to which the user is associated, generating, based on the mapping, a view including at least the one or more task data objects associated with the identified organization and not data objects associated with other organizations and displaying the view on a user interface.

Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency, such as accuracy of learning, accuracy of prediction, speed of learning, performance of learning, and energy efficiency of learning. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Each compute element has processing resources and memory resources. Each router enables communication via wavelets with at least nearest neighbors in a 2D mesh. Stochastic gradient descent, mini-batch gradient descent, and continuous propagation gradient descent are techniques usable to train weights of a neural network modeled by the processing elements. Reverse checkpoint is usable to reduce memory usage during the training.

Task delegation and cooperation for automated assistants is presented. A method comprises receiving, at a centralized support center that is in contact with a plurality of automated assistants including a first automated assistant and a second automated assistant, a request to perform a task on behalf of an individual, formulating, at the centralized support center, the task as a plurality of sub-tasks including a first sub-task and a second sub-task, delegating, at the centralized support center, the first sub-task to the first automated assistant, based on a determination at the centralized support center that the first automated assistant is capable of performing the first sub-task, and delegating, at the centralized support center, the second sub-task to the second automated assistant, based on a determination at the centralized support center that the second automated assistant is capable of performing the second sub-task.

A system and method for backing up workloads for multiple tenants of a cloud computing system are disclosed. A method of backing up workloads for multiple tenants of a computing system includes triggering an archival process according to an archival policy set by a tenant, and executing the archival process by reading backup data of the tenant stored in a backup storage device of the computer system and transmitting the backup data to an archival store designated in the archival policy, and then deleting or invalidating the backup data stored in the backup storage device.

Techniques are disclosed for scheduling artificial intelligence model partitions for execution in an information processing system. For example, a method comprises the following steps. An intermediate representation of an artificial intelligence model is obtained. A reversed computation graph corresponding to a computation graph generated based on the intermediate representation is obtained. Nodes in the reversed computation graph represent functions related to the artificial intelligence model, and one or more directed edges in the reversed computation graph represent one or more dependencies between the functions. The reversed computation graph is partitioned into sequential partitions, such that the partitions are executed sequentially and functions corresponding to nodes in each partition are executed in parallel.