A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

A radio frequency (RF) summer circuit having a characteristic impedance Z.sub.0 comprises first and second ports coupled by first and second resistances, respectively, to a junction. The circuit further comprises a series combination of a third resistance and a switch movable between open and closed positions and an amplifier having input and output terminals and operable in an off state and an on state wherein the series combination is coupled across the input and output terminals of the amplifier between the junction and a third port. The first resistance, second resistance, and the third resistance are all substantially equal to Z.sub.0/3. Further, when the switch is moved to the closed position and the amplifier is switched to the off state a passive mode of operation is implemented and when the switch is moved to the open position and the amplifier is switched to the on state an active mode of operation is implemented. The RF summer circuit develops a summed signal at the third port equal to a sum of signals at the first and second ports modified by one of first and second gain values.

A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

A radio frequency (RF) summer circuit having a characteristic impedance Zo comprises first and second ports coupled by first and second resistances, respectively, to a junction. The circuit further comprises a series combination of a third resistance and a switch movable between open and closed positions and an amplifier having input and output terminals and operable in an off state and an on state wherein the series combination is coupled across the input and output terminals of the amplifier between the junction and a third port. The first resistance, second resistance, and the third resistance are all substantially equal to Z.sub.0/3. Further, when the switch is moved to the closed position and the amplifier is switched to the off state a passive mode of operation is implemented and when the switch is moved to the open position and the amplifier is switched to the on state an active mode of operation is implemented. The RF summer circuit develops a summed signal at the third port equal to a sum of signals at the first and second ports modified by one of first and second gain values.

A waveform conversion unit (42) of a numerically controlled oscillator has a cosine table (101) and a sine table (102) in which parameters for cosine wave and sine wave signal generation are stored, a correction mechanism (50) for generating correction values according to the phase of an inputted phase signal, an adder (111) for generating a cosine wave signal from a parameter in the cosine table (101) and a correction value, and an adder (112) for generating a sine wave signal from a parameter in the sine table (102) and a correction value. The correction mechanism (50) uses waveform data which is a kind of parabolic data and whose phase interval is more minute than the phase interval of the parameters in each table (101), (102) to generate correction values for correcting cosine wave and sine wave signals to be found by linear interpolation.

A waveform conversion unit (42) of a numerically controlled oscillator has a cosine table (101) and a sine table (102) in which parameters for cosine wave and sine wave signal generation are stored, a correction mechanism (50) for generating correction values according to the phase of an inputted phase signal, an adder (111) for generating a cosine wave signal from a parameter in the cosine table (101) and a correction value, and an adder (112) for generating a sine wave signal from a parameter in the sine table (102) and a correction value. The correction mechanism (50) uses waveform data which is a kind of parabolic data and whose phase interval is more minute than the phase interval of the parameters in each table (101), (102) to generate correction values for correcting cosine wave and sine wave signals to be found by linear interpolation.

A sum-of-products calculation apparatus is provided. The sum-of-products calculation apparatus includes an analog-to-digital (A-to-D) conversion circuit having an encoder circuit and a plurality of inverters. Threshold voltages of the inverters are set according to classification threshold values of an activation function. The inverters generate a plurality of bit signals in response to an analog sum-of-products signal. The encoder circuit encodes the bit signals to generate a digital signal.

A sum-of-products calculation apparatus is provided. The sum-of-products calculation apparatus includes an analog-to-digital (A-to-D) conversion circuit having an encoder circuit and a plurality of inverters. Threshold voltages of the inverters are set according to classification threshold values of an activation function. The inverters generate a plurality of bit signals in response to an analog sum-of-products signal. The encoder circuit encodes the bit signals to generate a digital signal.

A radio frequency (RF) summer circuit having a characteristic impedance Zo comprises first and second ports coupled by first and second resistances, respectively, to a junction. The circuit further comprises a series combination of a third resistance and a switch movable between open and closed positions and an amplifier having input and output terminals and operable in an off state and an on state wherein the series combination is coupled across the input and output terminals of the amplifier between the junction and a third port. The first resistance, second resistance, and the third resistance are all substantially equal to Z.sub.0/3. Further, when the switch is moved to the closed position and the amplifier is switched to the off state a passive mode of operation is implemented and when the switch is moved to the open position and the amplifier is switched to the on state an active mode of operation is implemented. The RF summer circuit develops a summed signal at the third port equal to a sum of signals at the first and second ports modified by one of first and second gain values.

Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.