A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

An operation circuit and a chip pertaining to the field of integrated circuit design technology are disclosed by the present application. The circuit includes a capacitor charging/discharging module and an error amplification module electrically connected to the capacitor charging/discharging module. The capacitor charging/discharging module is configured to receive a first signal and a third signal that are external to the capacitor charging/discharging module and to output a feedback signal. The error amplification module is configured to receive the feedback signal and a second signal that is external to error amplification module and to output, based on the received feedback and second signals, a target signal to the capacitor charging/discharging module. In a steady state, values of the target, first, second and third signals satisfy a predefined mathematical relationship.

An operation circuit and a chip pertaining to the field of integrated circuit design technology are disclosed by the present application. The circuit includes a capacitor charging/discharging module and an error amplification module electrically connected to the capacitor charging/discharging module. The capacitor charging/discharging module is configured to receive a first signal and a third signal that are external to the capacitor charging/discharging module and to output a feedback signal. The error amplification module is configured to receive the feedback signal and a second signal that is external to error amplification module and to output, based on the received feedback and second signals, a target signal to the capacitor charging/discharging module. In a steady state, values of the target, first, second and third signals satisfy a predefined mathematical relationship.

An operation circuit and a chip pertaining to the field of integrated circuit design technology are disclosed by the present invention. The circuit includes a capacitor charging/discharging module and an error amplification module electrically connected to the capacitor charging/discharging module. The capacitor charging/discharging module is configured to receive first, second and third signals external to the capacitor charging/discharging module, and to output a reference signal and a feedback signal. The error amplification module is configured to receive the reference and feedback signals and output a target signal to the capacitor charging/discharging module based on the received reference and feedback signals. The first, second and third signals are all analog signals, and in a steady state, values of the target, first, second and third signals satisfy a predefined mathematical relationship.

An operation circuit and a chip pertaining to the field of integrated circuit design technology are disclosed by the present invention. The circuit includes a capacitor charging/discharging module and an error amplification module electrically connected to the capacitor charging/discharging module. The capacitor charging/discharging module is configured to receive first, second and third signals external to the capacitor charging/discharging module, and to output a reference signal and a feedback signal. The error amplification module is configured to receive the reference and feedback signals and output a target signal to the capacitor charging/discharging module based on the received reference and feedback signals. The first, second and third signals are all analog signals, and in a steady state, values of the target, first, second and third signals satisfy a predefined mathematical relationship.

Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

Provided is a sine wave multiplication device of simple configuration, broad input signal level range, and minimal fluctuation in characteristics due to temperature. A signal component that corresponds to a product of an input signal Si and the third harmonic wave of a first square wave W1 included in an output signal Su1; and a signal component that corresponds to a product of the input signal Si and the fifth harmonic wave of the first square wave W1 is canceled by: a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W2 included in an output signal Su2; and a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W3 included in an output signal Su3.

Provided is a sine wave multiplication device of simple configuration, broad input signal level range, and minimal fluctuation in characteristics due to temperature. A signal component that corresponds to a product of an input signal Si and the third harmonic wave of a first square wave W1 included in an output signal Su1; and a signal component that corresponds to a product of the input signal Si and the fifth harmonic wave of the first square wave W1 is canceled by: a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W2 included in an output signal Su2; and a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W3 included in an output signal Su3.

A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

A system for performing analog multiply-and-accumulate (MAC) operations employs at least one cross coupling capacitor processing unit (C3PU). A system includes a wordline to which an analog input voltage is applied, a voltage supply line having a supply voltage (VDD), a bitline, a clock signal line, a current integrator op-amp connected to the bitline and to the clock signal line, and a C3PU connected to the wordline. The C3PU includes a CMOS transistor and a capacitive unit. The capacitive unit includes a cross coupling capacitor and a gate capacitor. The cross coupling capacitor is connected between the wordline and the gate terminal of the CMOS transistor. The gate capacitor is connected between the gate terminal and ground. The CMOS transistor is configured to conduct a current that is proportional to voltage applied to the gate terminal.