A power converter including a compressor as a load includes a compensation current output (80) allowing compensation current (Ic), which compensates for leakage current (Ia), to flow. A controller (50) receives a detection signal from a rotational speed sensor (55) which senses the rotational speed of the compressor (CM). When the rotational speed has increased to a set rotational speed at which the leakage current (Ia) is lower than or equal to its limiting value (Lmax) (e.g., the limiting value specified under the Electrical Appliances and Materials Safety Act or by the IEC) in a state where the compensation current output (80) is off, the compensation current output (80) is switched from an on state to an off state. This may reduce the leakage current from the compressor with low power loss.

A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.

A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.

A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.

A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.

Apparatus and methods are described for providing a mixed-signal full-wave precision rectifier. In one example of the disclosed technology, a full-wave rectifier circuit includes a comparator configured to output a logic 1 or logic 0 by comparing an analog input signal to a reference voltage. The circuit further includes an analog switch with a control input coupled to the comparator output. A first input of the analog switch is coupled to the analog electrical input and a second input of the analog switch is coupled to a reference input voltage. The switch thus selects the input signal or the reference signal to output based on the output of the comparator. An amplifier is coupled to receive the analog switch output and generate a signal following the input in an inverting or a non-inverting mode depending on the selected analog switch output, thereby generating a rectified full-wave output of the analog input signal.