A high-gain, low power, electronic amplifier for amplification of a low magnitude voltage signal through a comparator-integrator amplification method for energy-aware applications is disclosed. The electronic amplifier comprises: a comparator arrangement with at least one comparator unit adapted to receive a first voltage signal to be amplified and a first feedback voltage signal, and to generate a first two-level voltage comparison signal; a integrator arrangement to receive the first two-level voltage comparison signal and generate a first amplifier output signal corresponding to an amplification of the voltage signal to be amplified; and a first feedback network to receive the first amplifier output signal and generate the first feedback voltage signal.

It is provided a signal processing system, comprising at least a first, a second and a third digital-to-analog converter (DAC); a processing unit configured for splitting a sampled signal into a first and a second signal corresponding to different frequency portions of the sampled signal, transmitting the first signal to the first DAC, splitting the second signal into a first and a second subsignal and transmitting the first subsignal to the second DAC and the second subsignal to the third DAC, the first subsignal corresponding to the real part of the second signal and the second subsignal corresponding to the imaginary part of the second signal; an IQ mixer configured for mixing an analog output signal of the second DAC and an analog output signal of the third DAC and a combiner for combining an analog output signal of the first DAC and an output signal of the IQ mixer.

Embodiments of the present disclosure are based on a recognition that some processors are configured with instructions to compute logarithms and exponents (i.e. some processors include log and exp circuits). Embodiments of the present disclosure are further based on an insight that the use of the existing log and exp circuits could be extended to compute certain other functions by using the existing log and exp circuits to transform from a Cartesian to a logarithmic domain and vice versa and performing the actual computations of the functions in the logarithmic domain, which may be computationally easier than performing the computations in the Cartesian domain.

Embodiments of the present disclosure are based on a recognition that some processors are configured with instructions to compute logarithms and exponents (i.e. some processors include log and exp circuits). Embodiments of the present disclosure are further based on an insight that the use of the existing log and exp circuits could be extended to compute certain other functions by using the existing log and exp circuits to transform from a Cartesian to a logarithmic domain and vice versa and performing the actual computations of the functions in the logarithmic domain, which may be computationally easier than performing the computations in the Cartesian domain.

A system includes a storage device containing machine instructions and a plurality of digital values of an oversampled sinuisoidal signal. The system also includes a core coupled to the storage. The core is configured to execute the machine instructions, wherein, when executed, the machine instructions cause the core to implement a sigma-delta modulator that retrieves the plurality of digital values from the storage device as input to the modulator. The sigma-delta modulator is configured compute an output bit stream. The system further includes an analog filter configured to receive the output bit stream from the core and to low-pass filter the output bit stream to produce a sinusoidal output signal.

According to one embodiment, a semiconductor amplifier circuit includes: a first amplifier circuit including first and second P-type transistors; a second amplifier circuit including first and second N-type transistors; and first to seventh current mirror circuits. The first and second current mirror circuits are connected to drains of the first and second P-type transistors. The third and fourth current mirror circuits are connected to drains of the first and second N-type transistors. The sixth current mirror circuit is connected to the first, fourth and fifth current mirror circuits. The seventh current mirror circuit is connected to the second, third and fifth current mirror circuits.