A method implemented by a data processing system for processing data items of a stream of data items, including: accessing a specification that represents the executable logic, wherein a state of the specification for a particular value of the key specifies one or more portions of the executable logic that are executable in that state; receiving, over an input device or port, data items of a stream of data; for a first one of the data items of the stream, identifying a first state of the specification for a value of the key associated with that first one of the data items; processing, by the data processing system, the first one of the data items according to one or more portions of executable logic that are represented in the specification as being associated with the first state.

A circuit for simulating a capacitance fuel probe, the circuit comprising: an input for receiving an alternating current (AC) excitation signal; an output for outputting an output signal representing a capacitance of the simulated fuel probe; a single reference capacitance; a first amplifier connected to the reference capacitance, the first amplifier being configured to cause a current flow through the reference capacitance; a second, variable gain, amplifier, the second, variable gain amplifier being configured to output an AC signal representing a multiple of the current flow through the reference capacitance, wherein the AC signal output by the second amplifier is used to generate the output signal.

A circuit for simulating a capacitance fuel probe, the circuit comprising: an input for receiving an alternating current (AC) excitation signal; an output for outputting an output signal representing a capacitance of the simulated fuel probe; a single reference capacitance; a first amplifier connected to the reference capacitance, the first amplifier being configured to cause a current flow through the reference capacitance; a second, variable gain, amplifier, the second, variable gain amplifier being configured to output an AC signal representing a multiple of the current flow through the reference capacitance, wherein the AC signal output by the second amplifier is used to generate the output signal.

A system and method predicts one or more next steps during the construction or editing of a graphical model having executable semantics. The one or more next steps being valid actions according to the executable semantics and/or syntax of the graphical model. The system and method presents ghost versions of the one or more next steps on a display of the graphical model. In response to user selection of a given ghost version, the system and method changes the selected ghost version into a completed action at the graphical model. The system and system may also update an in-memory representation of the graphical model with the completed action. The in-memory representation supporting execution of the graphical model.

Computer-based computational tools for use in determining spatial charge distributions for biological systems that include one or more biological membranes are provided. At least one of the biological membrane includes at least two regions having different electrical properties, e.g., the biological membrane can include a pore having a higher conductivity than the surrounding bulk membrane. In other cases, the membrane can include non-active and active regions, with conservative fields acting at the non-active regions and a combination of conservative and non-conservative fields acting at the active regions. The non-conservative fields can, for example, originate from differences in ionic concentrations of the type which generate Nernst potential differences across membranes. Using the computer-based computational tools, charge distributions not previously known to exist have been discovered, e.g., ring-shaped charge distributions in the vicinity of an active pore.

A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

An envelope behavioral model is developed and used in a system and method that simulates and predicts outputs of a non-linear component. An analyzer generates a test signal which is provided as input to the non-linear component. Model kernels representative of static and dynamic parts of the model are extracted from an output of the non-linear component responsive to the test signal. The dynamic part represents memory effects of the non-linear component. The model kernels are then used by a simulator to predict the output of the non-linear component responsive to signals of a modulation type.

An envelope behavioral model is developed and used in a system and method that simulates and predicts outputs of a non-linear component. An analyzer generates a test signal which is provided as input to the non-linear component. Model kernels representative of static and dynamic parts of the model are extracted from an output of the non-linear component responsive to the test signal. The dynamic part represents memory effects of the non-linear component. The model kernels are then used by a simulator to predict the output of the non-linear component responsive to signals of a modulation type.

A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

A system and method for electrical tree simulation based on a modification of a discharge avalanche model with an application of a charge simulation method to determine partial discharge data during the growth of electrical trees in an insulation system and a method of using the model to determine the remaining useful life of an insulation system.