A circuit for simulating a capacitance fuel probe, the circuit comprising: an input for receiving an alternating current (AC) excitation signal; an output for outputting an output signal representing a capacitance of the simulated fuel probe; a single reference capacitance; a first amplifier connected to the reference capacitance, the first amplifier being configured to cause a current flow through the reference capacitance; a second, variable gain, amplifier, the second, variable gain amplifier being configured to output an AC signal representing a multiple of the current flow through the reference capacitance, wherein the AC signal output by the second amplifier is used to generate the output signal.

A circuit for simulating a capacitance fuel probe, the circuit comprising: an input for receiving an alternating current (AC) excitation signal; an output for outputting an output signal representing a capacitance of the simulated fuel probe; a single reference capacitance; a first amplifier connected to the reference capacitance, the first amplifier being configured to cause a current flow through the reference capacitance; a second, variable gain, amplifier, the second, variable gain amplifier being configured to output an AC signal representing a multiple of the current flow through the reference capacitance, wherein the AC signal output by the second amplifier is used to generate the output signal.

A first network device executing a device simulation tool receives a selection of a second network device in a communications network. The first network device receives a selection of at least one use case, scenario or error condition associated with operation of the second network device or the communications network, and executes a network simulation of the communications network based on the at least one use case, scenario or error condition. The first network device generates a call flow diagram, which involves the selected second network device, based on the executed network simulation, and provides a graphical display of the generated call flow diagram.

The disclosed technology includes systems and methods for modeling signaling and/or connections in a mobile network, and specifically, the benefits of any optimization technique on the traffic including signals and/or connections in the mobile network. Embodiments can allocate signaling to specific applications (e.g., to determine which applications are chatty and which can cause problematic signaling), and/or to further model the optimizations or savings utilizing the disclosed traffic optimization technology. In some embodiments, to enable or enhance the performance of the data traffic and signal optimization for the network, the disclosed technology includes one or more fields (e.g., an expanded “CRCS” fields) that are calculated by, for example, a CRCS analysis core module, to define and identify at least: (1) whether a transaction causes a connection (and thus signaling); and (2) the number of connections that are reduced or saved by the disclosed embodiments of distributed caching and proxy system.

An improved tool and technique for performance quality testing of a synthesized controller or a controller-in-development is disclosed. A controller's performance in a test run within a simulation testing environment is quantitatively compared to an optimal performance parameter as defined in a controller performance model. Deviation between these compared results is recorded as an indicator of poor controller performance. Only deviating test results are recorded for review to guide further fine tuning or modifications of controller settings, and to save mass storage space. The controller performance test runs autonomously and may be automatically restarted should any failure within the simulation environment occur.

A method that includes disabling circuit paths in a circuit under test during transition fault testing (TFT) of valid timing paths of the circuit under test. The method then tests the circuit paths at slower clock speeds than the clock speed of the valid timing paths during TFT of the circuit paths. Finally, the method tests the circuit paths and the valid timing paths to facilitate testing of the circuit under test.

In response to receiving observed data of mixed observed variables, a mixed causality objective function, being suitable for continuous observed variables and discrete observed variables is determined, wherein the mixed causality objective function includes a causality objective function for continuous observed variables and a causality objective function for discrete observed variables and the fitting inconsistency is adjusted based on weighted factors of the observed variables. Then, the mixed causality objective function is optimally solved by using a mixed sparse causal inference, suitable for both continuous observed variables and discrete observed variables, using the mixed observed data under a constraint of a directed acyclic graph, to estimate causality among the observed variables.

A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.