A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). Typical off-die peripheral-circuit component could be an address decoder, a sense amplifier, a programming circuit, a read-voltage generator, a write-voltage generator, a data buffer, or a portion thereof.

A discrete three-dimensional (3-D) processor comprises stacked first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises at least a portion of a logic/processing circuit and an off-die peripheral-circuit component of the 3D-M array(s). The preferred 3-D processor can be used to compute non-arithmetic function/model. In other applications, the preferred 3-D processor may also be a 3-D configurable computing array, a 3-D pattern processor, or a 3-D neuro-processor.

The present disclosure is related to an optical encoder which is configured to provide precise coding reference data by feature recognition technology. To apply the present disclosure, it is not necessary to provide particular dense patterns on a working surface. The precise coding reference data can be generated by detecting surface features of the working surface.

The present disclosure provides an image processing method, an image processing device, an electronic apparatus and a readable storage medium. The image processing method includes: obtaining feature map data of an input image; extracting a feature region in the feature map data in accordance with a size of a convolution kernel; performing windowing processing on the feature region; and obtaining a windowed feature map of the input image in accordance with the feature region obtained after the windowing processing.

A method is described that includes loading an array of content into a two-dimensional shift register. The two-dimensional shift register is coupled to an execution lane array. The method includes repeatedly performing a first sequence including: shifting with the shift register first content residing along a particular row or column into another parallel row or column where second content resides and performing operations with a particular corresponding row or column of the execution lane array on the first and second content. The method also includes repeatedly performing a second sequence including: shifting with the shift register content from a set of first locations along a resultant row or column that is parallel with the rows or columns of the first sequence into a corresponding set of second locations along the resultant row or column. The resultant row or column has values determined from the operations of the first sequence.

A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, doubling a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration. The method also includes executing one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations. Another method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.

Methods, apparatus, systems and articles of manufacture are disclosed for scalable architectures for reference signature matching and updating. An example method for scalable architectures for reference signature matching and updating includes accessing site signatures to be compared to reference signatures from a first group of media sources. Determining if a first reference node is an owner of a first one of the site signatures. Comparing a neighborhood of site signatures including the first site signature to reference signatures in a first subset of reference signatures when the first reference node is the owner of the first site signature, the first subset of references signatures stored in a first memory partition associated with the first reference node. Not comparing site signature to reference signatures when the first reference node is not the owner of the first one of the site signatures.

Fabrication processing is executed in a chip of an image sensor. An image capturing device includes an image capturing unit (11) mounted on a vehicle and configured to generate image data by performing image capturing of a peripheral region of the vehicle, a scene recognition unit (214) configured to recognize a scene of the peripheral region based on the image data, and a drive control unit (12) configured to control drive of the image capturing unit based on the scene recognized by the scene recognition unit.

A data processing device and a computer-implemented method are configured to execute in parallel a data hub process (6) comprising at least a segmentation sub-process (61) which segments input data into data segments and at least one keying sub-process (62) which provides keys to the data segments creating keyed data segments, wherein the data hub process (6) stores the keyed data segments in a shared memory device (4) as shared keyed data segments and a plurality of processes in the form of computation modules (7) wherein each computation module (7) is configured to access the at least one shared memory device (4) to look for modulo-specific data segments which are shared keyed data segments that are keyed with at least one key which is specific for at least one of the computation modules (7) and to execute a machine learning method on the module-specific data segments, said machine learning method comprising data interpretation and classification methods using at least one pre-trained neuronal network (71) and to output the result of the executed machine learning method to the shared memory device (4) or another computation module.

A vehicular vision system includes at least one color camera disposed at a vehicle and having an image sensor operable to capture image data. A first system on chip (SoC) includes an image signal processor that receives captured image data and converts the received image data to converted data that is in a format suitable for machine vision processing. A second system on chip (SoC) receives captured image data and communicates display data to a display disposed in the vehicle, with the display data being in a format suitable for display of video images at the display. At startup of the vehicle, video images derived from the display data are displayed by the display within a time period following startup of the vehicle and machine vision data processing of converted data does not commence until after the display time period has elapsed following startup of the vehicle.