A fault-tolerant active matrix display device for avionics systems includes a panel glass, a set of source signal lines, and a set of gate signal lines. Each of the gate signal lines includes a first gate line end and a second gate line end on opposite sides of the panel glass. A source driver circuit is coupled to at least a portion of the source signal lines. A first gate driver circuit includes a first set of gate driver cells. Each of the gate driver cells of the first gate line driver circuit includes a gate line output connected to one of the set of gate signal lines at the first gate line end thereof. A second gate driver circuit includes a second set of gate driver cells.

A pixel of a display apparatus includes a light emitting device and a pixel circuit connected to first to third gate control lines and the light emitting device, the pixel circuit including first to fourth nodes. The pixel circuit includes a driving transistor connected to the first to third nodes, a first transistor connected to the first gate control line and the first and second nodes, a second transistor connected to the second gate control line, the second node, and a first driving voltage line, a third transistor connected to the first gate control line, the third node, and the fourth node, a fourth transistor connected to the first gate control line, the fourth node, and an initialization voltage line, a fifth transistor connected to the third gate control line, the third node, and a data line, and a storage capacitor between the first node and the fourth node.

Provided is a liquid crystal display device, including: a plurality of scanning connection lines formed on at least one side of edges of the image display region, the plurality of scanning connection lines connecting together a scanning signal drive circuit and a plurality of scanning signal lines; a selection circuit formed so as to be interposed between the plurality of scanning connection lines and the plurality of scanning signal lines, the selection circuit being configured to selectively short-circuit one of a plurality of the scanning signal lines to one of the plurality of scanning connection lines based on a selection signal; and a selection signal line connected to the selection circuit, the selection signal line transmitting the selection signal to the selection circuit.

The present disclosure provides a pixel circuit, a pixel driving method and a display device. The pixel circuit includes a first initialization circuit and a compensation circuit; the first initialization circuit is configured to write a first initial voltage into the driving control node under the control of an initial control signal; the compensation circuit is configured to control the driving control node to be connected to the first node under the control of a compensation control signal. The first initialization circuit or the compensation circuit includes an oxide thin film transistor; or, one of the first initialization circuit and the compensation circuit includes a low temperature polysilicon thin film transistor and an oxide transistor connected in series, and the other of the first initialization circuit and the compensation circuit includes an oxide thin film transistor.

A display device including: first and second scan drivers; a data driver; a display unit including pixels connected to first and second scan lines, and data lines; and a controller controlling the first and second scan drivers, and the data driver, a first pixel includes: a light emitting element, a first transistor including a gate connected to a first node, wherein the first transistor is connected between a second node and a third node, a second transistor including a gate connected to a first scan line, the second transistor is connected between a data line and the second node, and a storage capacitor connected between the first node and a first power voltage; the first transistor is reverse biased by a second scan signal applied to a second scan line; and a first scan signal applied to the first scan line is different from the second scan signal.

A pixel includes a light emitting element, a driving switching element and a first compensation switching element and a second compensation switching element. The driving switching element is which applies a driving current to the light emitting element. The first compensation switching element and the second compensation switching element are connected between a control electrode of the driving switching element and an output electrode of the driving switching element. The first compensation switching element and the second compensation switching element are connected to each other in series. The driving switching element is a P-type transistor. The first compensation switching element is an N-type transistor. The second compensation switching element is a P-type transistor.

Embodiments of the disclosed subject matter provide a device that includes an organic light emitting device (OLED), and a drive circuit to control the operation of the OLED, comprising a response time accelerator thin film transistor (TFT) configured to short or reverse bias the OLED for a predetermined period of time during a frame time. Other embodiments include an OLED having a plurality of sub-pixels, where one or more of sub-pixels configured to emit light of at least a first color comprises a first emissive area and a second emissive area that are independently controllable, where the first emissive area is larger than the second emissive area. The controller is configured to control the second emissive area to have (i) a higher brightness, and/or (ii) a higher current density than the first emissive area for a first sub-pixel luminance level that is less than a maximum luminance.

A semiconductor device includes first to tenth transistors and first to fourth capacitors. Gates of the first and the fourth transistors are electrically connected to each other. First terminals of the first, second, fifth, and eighth transistors are electrically connected to a first terminal of the fourth capacitor. A second terminal of the fifth transistor is electrically connected to a gate of the sixth transistor and a first terminal of the second capacitor. A second terminal of the eighth transistor is electrically connected to a gate of the ninth transistor and a first terminal of the third capacitor. Gates of the second, seventh, and tenth transistors are electrically connected to first terminals of the third and fourth transistors and a first terminal of the first capacitor. First terminals of the sixth and seventh transistors are electrically connected to a second terminal of the second capacitor.

To provide a display device capable of displaying a plurality of images by superimposition using a plurality of memory circuits provided in a pixel. A plurality of memory circuits are provided in a pixel, and signals corresponding to images for superimposition are retained in each of the plurality of memory circuits. In the pixel, the signals corresponding to the images for superimposition are added to each of the plurality of memory circuits. The signals are added to the signals retained in the memory circuits by capacitive coupling. A display element can display an image corresponding to a signal in which a signal written to a pixel through a wiring is added to the signals retained in the plurality of memory circuits. Reduction in the amount of arithmetic processing for displaying images by superimposition can be achieved.

The present application provides a simultaneous emission pixel compensation circuit and a display panel. Through adopting a transistor with a double-gate structure as a driving transistor, and through a bottom gate to regulate a threshold voltage of the driving transistor, compensation of positive and negative drift of the threshold voltage of the driving transistor is realized. Through introducing simultaneous emission technology and adopting a global signal to perform corresponding control, a number of a scan signal to scan row by row is decreased to only one, such that a circuit structure is simple and a number of transistors required is less, thereby facilitating integration in a panel.