A pixel circuit includes a data writing sub-circuit and a leakage prevention sub-circuit. The data writing sub-circuit is coupled to a first scan signal terminal, a data signal terminal and a light-emitting control sub-circuit, and is configured to: in a data writing period, store a light-emitting compensation signal in response to a gate scan signal from the first scan signal terminal and a data signal from the data signal terminal; and in a light-emitting period, assist in controlling the light-emitting control sub-circuit to be turned on according to the light-emitting compensation signal. The leakage prevention sub-circuit is coupled to the data writing sub-circuit and an auxiliary voltage terminal that is configured to provide to a constant voltage, and is configured to: in the data writing period, store another light-emitting compensation signal; and in the light-emitting period, inhibit leakage of the data writing sub-circuit according to the another light-emitting compensation signal.

Display panel, light sensing detection method thereof and display device are provided. The display panel includes a plurality of light sensing detection units. A light sensing detection unit of the plurality of light sensing detection units includes a light sensing detection circuit. The light sensing detection circuit corresponding to a same light sensing detection unit includes N light sensing detection branches connected in parallel, a light sensing detection branch of the N light sensing detection branches includes a storage capacitor, and N≥2. The N light sensing detection branches include a first light sensing detection branch and a second light sensing detection branch. The storage capacitor includes a first storage capacitor located in the first light sensing detection branch and a second storage capacitor located in the second light sensing detection branch. A capacitance of the first storage capacitor is greater than a capacitance of the second storage capacitor.

A display device includes a display panel, a data driving circuit, and a timing controller, wherein the display panel includes a plurality of gate lines to which a scan signal is applied, a plurality of data lines to which a data voltage is applied, a plurality of reference voltage lines to which a reference voltage is applied, and a plurality of subpixels, wherein the data driving circuit senses a voltage on one reference voltage line selected from the plurality of reference voltage lines in a first detecting period and a second detecting period having different voltage detecting paths, and wherein the timing controller controls the data driving circuit, and determining whether or not the reference voltage line is abnormal using a sensing voltage detected from the reference voltage line.

A display device includes a display panel including a first partial panel region and a second partial panel region, and a panel driver which drives the display panel. The panel driver determines a first driving frequency for the first partial panel region and a second driving frequency for the second partial panel region. In a case where the first driving frequency and the second driving frequency are different from each other, the panel driver sets a boundary portion including a boundary between the first partial panel region and the second partial panel region, and determines a third driving frequency for the boundary portion to be between the first driving frequency and the second driving frequency.

A display device includes a scan line extending in a direction, a data line and a driving voltage line extending in another direction, a transistor electrically connected to the driving voltage line and including a first gate electrode and a first semiconductor layer, a second transistor electrically connected to the scan and data lines and including a second gate electrode and a second semiconductor layer, a first capacitor electrically connected to the first transistor and including first and second capacitor plates, and a second capacitor including a third capacitor plate electrically connected to the first transistor and a fourth capacitor plate electrically connected to the second transistor. The second capacitor plate includes a first hole overlapping the first capacitor plate, the fourth capacitor plate includes a second hole overlapping the third capacitor plate, and a size of the second hole is different from that of the first hole.

An organic light emitting diode display device includes: a substrate including a plurality of sub-pixels classified into a plurality of horizontal pixel lines; a gate line and a sensing line spaced apart from each other on the substrate; a data line and a power line crossing the gate line and the sensing line and spaced apart from each other; and first and second reference lines supplying first and second reference voltages, respectively, and connected to adjacent two, respectively, of the plurality of horizontal pixel lines.

A pixel compensation device includes a controller and at least one external compensation circuit. In the external compensation circuit, a first input circuit is configured to transmit a first voltage to a first terminal of a driving sub-circuit in a initialization phase, perform blanking in a pre-storage phase, and transmit a threshold compensation voltage to the first terminal in the data compensation writing phase; a second input circuit is configured to transmit a second voltage to a control terminal of the driving sub-circuit in the initialization phase and the pre-storage phase, so that a voltage of the first terminal changes from the first voltage to the threshold compensation voltage in the pre-storage phase; a sensing circuit is configured to sense the threshold compensation voltage in the data compensation writing phase; and the controller is configured to transmit a data voltage to the control terminal in the data compensation writing phase.

Provided is a pixel driving circuit configured to provide a signal to a to-be-driven element. The pixel driving circuit includes: a current control sub-circuit, configured to transmit a current signal; a time length control sub-circuit, configured to transmit a time signal; and an output sub-circuit, electrically connected with the time length control sub-circuit and the current control sub-circuit, respectively; where the time length control sub-circuit is further configured to control the output sub-circuit to be turned on or off based on the time signal; the output sub-circuit is configured to, when turned on, control a current applied to the to-be-driven element based on the current signal, where duration of two adjacent turn-ons of the output sub-circuit is same and duration of two adjacent turn-offs of the output sub-circuit is same.

A shift register unit includes a first input/output unit which includes a first pull-down control circuit and a first auxiliary input circuit, and a second input/output unit which includes a second pull-down control circuit and a second auxiliary input circuit. The first pull-down control circuit controls a level of a first pull-down node. The first auxiliary input circuit is coupled to the first pull-down control circuit and controls the first pull-down control circuit together with a level of a first pull-up node in response to a display control signal and a blanking control signal. The second pull-down control circuit controls a level of a second pull-down node. The second auxiliary input circuit is coupled to the second pull-to down control circuit and controls the second pull-down control circuit together with a level of a second pull-up node in response to the display control signal and the blanking control signal.

A pixel driving circuit includes: an energy storage sub-circuit, a reset sub-circuit, a compensation sub-circuit, a driving sub-circuit, and a current leakage suppression sub-circuit. The energy storage sub-circuit is coupled to a first node and a second node. The reset sub-circuit is coupled to the second node, a first scan timing signal terminal, and an initialization signal terminal. The compensation sub-circuit is coupled to the second node, a third node, and a second scan timing signal terminal. The driving sub-circuit is coupled to the second node, the third node, and a first voltage signal terminal. The current leakage suppression sub-circuit is coupled to the energy storage sub-circuit, the reset sub-circuit, and the compensation sub-circuit. The current leakage suppression sub-circuit is configured to suppress current leakage of the energy storage sub-circuit in a process of generating and transmitting the driving signal by the driving sub-circuit.