An organic light emitting diode display device includes: a substrate including a plurality of sub-pixels classified into a plurality of horizontal pixel lines; a gate line and a sensing line spaced apart from each other on the substrate; a data line and a power line crossing the gate line and the sensing line and spaced apart from each other; and first and second reference lines supplying first and second reference voltages, respectively, and connected to adjacent two, respectively, of the plurality of horizontal pixel lines.

Disclosed is an electroluminescent display device using a variable refresh rate (VRR) mode. The purpose of the present disclosure is to reduce the occurrence of a difference in luminance at a time point of a refresh rate change, thereby preventing viewers from perceiving the variation of the refresh rate.

A light emitting display device includes a display panel including a first pixel group including a plurality of pixels in 2N rows. The light emitting display device further includes a second pixel group disposed subsequent to the first pixel group and including a plurality of pixels in 2N rows. The light emitting display device further includes an emission signal unit including a first emission stage for applying the same first emission signal to the first pixel group and a second emission stage for applying the same second emission signal to the second pixel group. In a first frame, a falling time of the first emission signal and a rising time of the second emission signal are different from each other.

A display device includes a display panel including a plurality of pixels. At least one of the pixel includes a light emitting diode, a first transistor connected between a power line receiving a power source voltage and an anode of the light emitting diode, a second transistor connected between a data line and a first reference node, a first capacitor connected between the power line and the first reference node, a second capacitor connected between the first reference node and a second reference node, a third transistor connected between the first reference node and a reference voltage line receiving a reference voltage, a fourth transistor connected between an initialization voltage line receiving an initialization voltage and a drain of the first transistor, and a fifth transistor connected between the drain of the first transistor and the anode of the light emitting diode.

A light emitting apparatus comprising a plurality of pixels with different light emitting colors, each of the plurality of pixels includes a light-emitting element configured to emit light with one of at least three different light emitting colors, a driving transistor configured to supply a current to the light-emitting element in accordance with a voltage supplied to a gate, a write transistor configured to supply a signal voltage from a signal line to the gate of the driving transistor, and a capacitance at a connection portion between the driving transistor and the write transistor, wherein the capacitance is different for each light emitting color, and is larger in a pixel of a light emitting color in which a peak current flowing through the light-emitting element is larger.

A display device includes a first light-emitting element disposed in a first display area, a second light-emitting element disposed in a second display area, a first pixel circuit disposed in the first display area, where the first pixel circuit output a first driving current for driving at least one selected from the first light-emitting element and the second light-emitting element, a first emission control transistor which connects the first pixel circuit to the first light-emitting element, and a second emission control transistor which connects the first pixel circuit to the second light-emitting element.

The techniques disclosed herein provide apparatus, methods and systems that adaptively adjust the signal waveform (or waveshape) of the drive signal to a slow-scan mirror to compensate for non-linearities observed in the slow-scan feedback signal from a slow-scan mirror. Over large scan angles and high temperatures, the slow-scan mirror in a laser beam scanning device may exhibit a nonlinear response to the drive signal that results in poor image quality issues such as bright lines, bands in the display image, and image distortion. The presently disclosed technologies track the linearity performance of the overall system by detecting non-linearities in waveform of the slow-scan feedback signal real time, and consequently apply a pre-distortion to the drive waveform to compensate for these detected non-linearities. The parameters, logic and blocks of the control may be implemented in hardware, software or combinations thereof.

A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

A light emitting display device includes a pixel circuit unit, a data distribution unit, a plurality of signal generating units, a unit light emitting diode, and a dummy opening. The pixel circuit unit is configured to generate an output current. The data distribution unit is configured to apply a data voltage to the pixel circuit unit through a data line. The plurality of signal generating units are respectively configured to apply a scan signal and a light emission control signal to the pixel circuit unit through a plurality of signal lines. The unit light emitting diode is configured to receive the output current of the pixel circuit unit and is attached to the pixel circuit unit. The dummy opening is formed in the region where the pixel circuit unit, the data distribution unit, and a plurality of signal generating units are not positioned.

A display can include a plurality of pixels arranged in a matrix of rows and columns, and a gate driver circuit including a plurality of row drivers configured as a shift register that sequentially and individually addresses the rows. The display panel can also include a first clock circuit configured to provide a first set of clock signals to a first portion of the row drivers to address a respective first portion of the rows. The first clock circuit can include a signal distribution circuit having a first input impedance. The display panel can also include a second clock circuit configured to provide a second set of clock signals to a second portion of the row drivers to address a respective second portion of the rows. The second clock circuit can include a signal distribution circuit having a second input impedance that is matched with the first input impedance.