A display device includes a display panel including a first display area; a second display area protruding in a first direction from the first display area; and a first non-display area adjacent to a side of the second display area. Each of the first display area and the second display area includes subpixels that display an image and scan lines electrically connected to the subpixels. The first non-display area includes dummy pixels; a common scan line electrically connected to the dummy pixels; load matching switch elements respectively disposed between the scan lines and the common scan line; and a load matching driving circuit that outputs load matching control signals to control turn-on and turn-off of the load matching switch elements.

A liquid crystal display device comprises a display panel, at least one signal generator, and a plurality of wires. The display panel has a plurality of input ends to receive data signal. The at least one signal generator has a plurality of output ends to supply the data signal to the input ends of the display panel, respectively. The wires connects the output ends of the at least one signal generator to the input ends of the display panel, respectively, the wires having lengths measured between the output ends of the at least one signal generator and the input ends of the display panel, respectively, the length of the wires being different from each other according to location of the output ends of the at least one signal generator.

A display device and a driving method thereof are discussed. The display device can include a display panel for displaying images, a scan driver for supplying scan signals to the display panel, and a gate compensation circuit. The gate compensation circuit is configured to respectively sense a first node voltage and a second node voltage from a first node controller and a second node controller of the scan driver, and change a turn-on duty ratio of the first node controller to the second node controller based on the sensed first node voltage and second node voltage.

The present disclosure relates to a circuit of controlling a common voltage of a liquid crystal panel. According to an embodiment of the present disclosure, a voltage control circuit is configured to provide a common voltage to a common electrode of a liquid crystal panel. The liquid crystal panel includes M rows and N columns of pixel units. Each pixel unit is coupled to the common electrode. The voltage control circuit includes an operational amplifier arranged in a negative feedback configuration. The operational amplifier includes: an input stage, a gain stage and an output stage. The output stage includes a second NMOS transistor and a second PMOS transistor. A gate of the second NMOS transistor receives a first control signal, a drain of the second NMOS transistor is coupled to a gate of a first PMOS transistor, and a source of the second NMOS transistor is coupled to a second reference voltage. A gate of the second PMOS transistor receives a second control signal, a drain of the second PMOS transistor is coupled to a gate of a first NMOS transistor, and a source of the second PMOS transistor is coupled to a third reference voltage.

A display backplane is provided, including a base, wherein pixel circuits, bonding electrodes, and bonding connection wires are on the base; the bonding electrodes are coupled to the bonding connection wires in a one-to-one correspondence; the bonding electrodes and the bonding connection wires are on two opposite surfaces of the base; the pixel circuits and the bonding connection wires are on a same side of the base; one end of each bonding connection wire is coupled to the bonding electrode through the first via in the base; the other end of each of at least some bonding connection wires is coupled to the pixel circuit; and an orthographic projection of at least one of the bonding electrodes and the bonding connection wires on the base is not coincident with an orthographic projection of the pixel circuit on the base.

The present disclosure provides an array substrate and a display device. The array substrate includes one start data line, N−1 intermediate data line and one end data line. The array substrate further includes a first driving circuit and a second driving circuit, the first driving circuit is arranged at a first side of the plurality of data lines, and the second driving circuit is arranged at a second side of the plurality of data lines opposite to the first side in a first direction. The first driving circuit is electrically connected to the first end of each of the plurality of data lines. The first driving circuit is electrically coupled to first ends of the plurality of data lines, a first end of the end data line is electrically coupled to a first end of the start data line, and the second driving circuit is electrically coupled to second ends of the plurality of data lines.

A display device includes: a display panel including a display area including pixels and a non-display area including a dummy pixel; a scan driver which supplies a scan signal to the display panel; a data driver which supplies a data signal to the display panel; and a timing controller which supplies a first control signal for controlling the scan driver and a second control signal for controlling the data driver. The dummy pixel is connected to a bad pixel among the pixels in the display area through a repair line, and a connection of the dummy pixel to the repair line is cut off in an initialization phase in which a voltage of an initialization power source is supplied.

The disclosure includes multiple data drivers provided for each predetermined number of data lines. Each data driver receives an image signal; generates, based on the image signal, a positive gradation data signal and a negative gradation data signal; outputs one of the positive and negative gradation data signals to one of a first and second data line groups of a display panel; and outputs the other of the positive and negative gradation data signals to the other of the first and second data line groups. The data driver shifts a phase of the negative gradation data signal in a direction delayed with respect to the positive gradation data signal, and controls a slew rate of an output amplifier for outputting the positive gradation data signal to be lower than that of an output amplifier for outputting the negative gradation data signal.

A display module includes a display panel in which a plurality of pixels each including a plurality of sub-pixels are disposed on a plurality of row lines; and a driver. The driver is configured to set a PWM data voltage to the plurality of sub-pixels included in the plurality of row lines in a row line sequence, apply a sweep signal, which is a voltage signal sweeping between two different voltages, to sub-pixels among the plurality of sub-pixels that are included in at least some consecutive row lines among the plurality of row lines in the row line sequence, and drive the display panel to cause the sub-pixels included in the at least some consecutive row lines to emit light based on the PWM data voltage in the row line sequence.

A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.