A pixel circuit includes a data writing sub-circuit and a leakage prevention sub-circuit. The data writing sub-circuit is coupled to a first scan signal terminal, a data signal terminal and a light-emitting control sub-circuit, and is configured to: in a data writing period, store a light-emitting compensation signal in response to a gate scan signal from the first scan signal terminal and a data signal from the data signal terminal; and in a light-emitting period, assist in controlling the light-emitting control sub-circuit to be turned on according to the light-emitting compensation signal. The leakage prevention sub-circuit is coupled to the data writing sub-circuit and an auxiliary voltage terminal that is configured to provide to a constant voltage, and is configured to: in the data writing period, store another light-emitting compensation signal; and in the light-emitting period, inhibit leakage of the data writing sub-circuit according to the another light-emitting compensation signal.

A display device includes a display panel, a data driving circuit, and a timing controller, wherein the display panel includes a plurality of gate lines to which a scan signal is applied, a plurality of data lines to which a data voltage is applied, a plurality of reference voltage lines to which a reference voltage is applied, and a plurality of subpixels, wherein the data driving circuit senses a voltage on one reference voltage line selected from the plurality of reference voltage lines in a first detecting period and a second detecting period having different voltage detecting paths, and wherein the timing controller controls the data driving circuit, and determining whether or not the reference voltage line is abnormal using a sensing voltage detected from the reference voltage line.

A display panel and a display device are provided. The display panel includes a pixel circuit; and a light-emitting element. The operation process of the pixel circuit includes a first data refresh period, a data adjustment stage, and a second data refresh period set in sequence. The data adjustment stage includes T1 first sub-data adjustment stages set in sequence and T2 second sub-data adjustment stages set in sequence. A quantity of the data writing frames in the first sub-data adjustment stage is greater than a quantity of the data writing frames in the second sub-data adjustment stage. A quantity of the holding frames in the first sub-data adjustment stage is smaller than a quantity of the holding frames in the second sub-data adjustment stage.

The present disclosure relates to the technical field of display panels, in particular to a driving method and driving apparatus of a display panel. The driving method may include in response to detecting that the display panel is switched from a dynamic picture to a static picture, generating a refresh rate adjustment instruction; according to the refresh rate adjustment instruction, switching the picture refresh rate of the display panel from a first picture refresh rate to a second picture refresh rate and generating a voltage adjustment instruction; obtaining a target cathode power supply voltage matching the second picture refresh rate; and based on the voltage adjustment instruction and the target cathode power supply voltage, adjusting the display panel to change a working current of each pixel in the display panel.

A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

Provided is a pixel driving circuit configured to provide a signal to a to-be-driven element. The pixel driving circuit includes: a current control sub-circuit, configured to transmit a current signal; a time length control sub-circuit, configured to transmit a time signal; and an output sub-circuit, electrically connected with the time length control sub-circuit and the current control sub-circuit, respectively; where the time length control sub-circuit is further configured to control the output sub-circuit to be turned on or off based on the time signal; the output sub-circuit is configured to, when turned on, control a current applied to the to-be-driven element based on the current signal, where duration of two adjacent turn-ons of the output sub-circuit is same and duration of two adjacent turn-offs of the output sub-circuit is same.

A pixel driving circuit includes: an energy storage sub-circuit, a reset sub-circuit, a compensation sub-circuit, a driving sub-circuit, and a current leakage suppression sub-circuit. The energy storage sub-circuit is coupled to a first node and a second node. The reset sub-circuit is coupled to the second node, a first scan timing signal terminal, and an initialization signal terminal. The compensation sub-circuit is coupled to the second node, a third node, and a second scan timing signal terminal. The driving sub-circuit is coupled to the second node, the third node, and a first voltage signal terminal. The current leakage suppression sub-circuit is coupled to the energy storage sub-circuit, the reset sub-circuit, and the compensation sub-circuit. The current leakage suppression sub-circuit is configured to suppress current leakage of the energy storage sub-circuit in a process of generating and transmitting the driving signal by the driving sub-circuit.

A four-way dual scanning electronic display board capable of scan control, whereby, in order to provide drive control, an LED module arrangement method, and processing for each LED pixel dot (R, G, B), which are for easily enabling a high definition image, pixel display dots of an LED module are controlled by processing image display dots of the module by means of a four-way method by an automatic image switching device through the display control of SCU image switching, in order to display a high definition image through the four-way control of each image dot (R, G, B) pixel, and thus high resolution image quality may be enabled and displayed.

A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, and the driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, and the non-light-emitting stage includes a bias adjustment stage, in which one of a source and a drain of the driving transistor receives a bias adjustment signal. An operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2. A working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame.

A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.