In one embodiment, a computing system may determine a group of subpixels, that are associated with different color channels, within a display region of a display. The system may determine a micro-pixel corresponding to a basic unit shape configured to evenly divide the display region and each subpixel. The system may represent the display region as a group of micro-pixels and each subpixel as a combination of one or more micro-pixels in the group of micro-pixels. The system may determine a constraint for each color channel of the display region based on the group of micro-pixels. The constraint may constrain the micro-pixels associated with a same subpixel to have a same color value. The system may generate, based on an optimization process using the constraint, a filter for the display region. The filter may be configured to adjust image pixel values to be displayed by the group of subpixels.

A method of controlling a display device includes obtaining a duty cycle of a backlight control signal, and adjusting a starting time of a pulse in the backlight control signal at least according to the duty cycle. The backlight control signal is used to control a backlight of the display device.

In various examples, a low-latency variable backlight liquid crystal display (LCD) system is disclosed. The LCD system may reduce latency and video lag by performing an analysis of peak pixel values within subsets of pixels using a rendering device, prior to transmitting the frame to a display device for display. As a result, the display device may receive the peak pixel value data prior to or concurrently with the frame data, and may begin updating the backlight settings of the display without having to wait for a substantial portion of the frame to be received. In this way, the LCD system may avoid the full frame delay of conventional systems, allowing the LCD system to more reliably support high-performance applications such as gaming.

In various examples, a low-latency variable backlight liquid crystal display (LCD) system is disclosed. The LCD system may reduce latency and video lag by performing an analysis of peak pixel values within subsets of pixels using a rendering device, prior to transmitting the frame to a display device for display. As a result, the display device may receive the peak pixel value data prior to or concurrently with the frame data, and may begin updating the backlight settings of the display without having to wait for a substantial portion of the frame to be received. In this way, the LCD system may avoid the full frame delay of conventional systems, allowing the LCD system to more reliably support high-performance applications such as gaming.

The present invention overcomes image defects such as the brightness inclination or smears by reducing the line resistance of a power source bus line which supplies electricity to organic EL elements. A plurality of pixels which are arranged in a matrix array is connected to power source lines, and the plurality of power source lines are connected to a power source bus line. Both ends of the power source bus line are connected to a power source part via a FPC. By supplying electricity to both ends of the power source bus line from the power source part, the line resistance of the power source bus line can be reduced.

A display can include a plurality of pixels arranged in a matrix of rows and columns, and a gate driver circuit including a plurality of row drivers configured as a shift register that sequentially and individually addresses the rows. The display panel can also include a first clock circuit configured to provide a first set of clock signals to a first portion of the row drivers to address a respective first portion of the rows. The first clock circuit can include a signal distribution circuit having a first input impedance. The display panel can also include a second clock circuit configured to provide a second set of clock signals to a second portion of the row drivers to address a respective second portion of the rows. The second clock circuit can include a signal distribution circuit having a second input impedance that is matched with the first input impedance.

A pixel includes: a light emitting element; a first transistor which drives the light emitting element; a second transistor electrically connected between a gate node of the first transistor and a data line; a third transistor electrically connected between a first node of the first transistor and an initialization voltage line; and a storage capacitor electrically connected between the gate node and the first node of the first transistor. Here, upon an operation in a variable frame mode, an initialization voltage is applied to the initialization voltage line, and the initialization voltage has a first voltage level. In addition, in a data writing period during which the storage capacitor is charged with an electric charge, the initialization voltage further includes a pulse voltage such that the initialization voltage has a second voltage level that is greater than the first voltage level.

A method for driving an active matrix organic light-emitting diode (AMOLED) display. The method may be used to digitally drive the AMOLED display in a way that limits the susceptibility of the AMOLED display to certain problems arising out of digital driving techniques, such as image sticking or low display lifetimes. The method involves generating compensation factors corresponding to each pixel of the display and using those compensation factors to control the illumination of the display. The aspects of the method that incorporate the operation point for generating a compensation factor may also be applied to analog driving of AMOLED displays.

A pixel includes: a light emitting element; a first transistor which drives the light emitting element; a second transistor electrically connected between a gate node of the first transistor and a data line; a third transistor electrically connected between a first node of the first transistor and an initialization voltage line; and a storage capacitor electrically connected between the gate node and the first node of the first transistor. Here, upon an operation in a variable frame mode, an initialization voltage is applied to the initialization voltage line, and the initialization voltage has a first voltage level. In addition, in a data writing period during which the storage capacitor is charged with an electric charge, the initialization voltage further includes a pulse voltage such that the initialization voltage has a second voltage level that is greater than the first voltage level.

The present invention overcomes image defects such as the brightness inclination or smears by reducing the line resistance of a power source bus line which supplies electricity to organic EL elements. A plurality of pixels which are arranged in a matrix array is connected to power source lines, and the plurality of power source lines are connected to a power source bus line. Both ends of the power source bus line are connected to a power source part via a FPC. By supplying electricity to both ends of the power source bus line from the power source part, the line resistance of the power source bus line can be reduced.