The present disclosure relates to a circuit of controlling a common voltage of a liquid crystal panel. According to an embodiment of the present disclosure, a voltage control circuit is configured to provide a common voltage to a common electrode of a liquid crystal panel. The liquid crystal panel includes M rows and N columns of pixel units. Each pixel unit is coupled to the common electrode. The voltage control circuit includes an operational amplifier arranged in a negative feedback configuration. The operational amplifier includes: an input stage, a gain stage and an output stage. The output stage includes a second NMOS transistor and a second PMOS transistor. A gate of the second NMOS transistor receives a first control signal, a drain of the second NMOS transistor is coupled to a gate of a first PMOS transistor, and a source of the second NMOS transistor is coupled to a second reference voltage. A gate of the second PMOS transistor receives a second control signal, a drain of the second PMOS transistor is coupled to a gate of a first NMOS transistor, and a source of the second PMOS transistor is coupled to a third reference voltage.

This application provides an electronic device, to reduce a probability that a screen stalling phenomenon. A timing control unit sends one first pulse of a tearing effect signal every a first preset time T1. The timing control unit sends S second pulses of the tearing effect signal when a transceiver unit does not receive an N.sup.th frame of display data within a preset time. The processing unit receives the N.sup.th frame of display data in the (N+1).sup.th frame, and controls, based on the N.sup.th frame of display data, the display to display an N.sup.th frame of image.

A pixel includes a first capacitor connected between first and second nodes, a second capacitor connected between a first voltage line and the first node, a light emitting diode including a first electrode and a second electrode connected with a second voltage line, a first transistor including a first electrode, a second electrode, and a gate electrode connected with the second node, a second transistor including a first electrode, a second electrode, and a gate electrode which receives a scan signal, a third transistor including a first electrode, a second electrode, and a gate electrode which receives a first compensation scan signal, a fourth transistor including a first electrode, a second electrode, and a gate electrode which receives a second compensation scan signal, and a fifth transistor including a first electrode, a second electrode, and a gate electrode which receives a first light emitting signal.

A pixel of an OLED display device includes a capacitor coupled between first and second nodes, first and second transistors, each including a gate receiving a respective initialization signal, a first terminal receiving a first power supply voltage, and a second terminal coupled to the capacitor, a third transistor including a first terminal coupled to a data line and a second terminal coupled to the first node, a fourth transistor including a gate coupled to the second node, a first terminal receiving the first power supply voltage, and a second terminal coupled to a third node, a fifth transistor including a first terminal coupled to the third node and a second terminal coupled to the second node, sixth and seventh transistors receiving a scan signal, eighth and ninth transistors receiving an emission signal, and an OLED.

A driving controller includes an oscillator and a signal generator. The oscillator is configured to generate an oscillation signal based on an input current. The signal generator is configured to generate a gate driving signal and a data driving signal based on the oscillation signal. The oscillator is configured to maintain a frequency of one horizontal period of the oscillation signal to be constant when an oscillation fundamental frequency is shifted. When the oscillation fundamental frequency is f0 and a fundamental constant is N0, the frequency of one horizontal period is f0/N0.

A pixel circuit and a display device including the same are disclosed. The pixel circuit of this disclosure includes a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to supply an electric current to a light emitting element; a first switch element configured to be turned on according to a gate-on voltage of a scan pulse to supply a data voltage to the second node; and a second switch element configured to be turned off according to a gate-off voltage of a light emitting control pulse generated in antiphase of the scan pulse.

A pixel circuit and a display device including the pixel circuit are disclosed. The pixel circuit according to embodiments includes a first pixel circuit connected in parallel to an initialization voltage line to which an initialization voltage is applied, and including a first-first switch element connected to a first-first gate line and a first-second switch element connected to a first-second gate line; and a second pixel circuit connected in parallel to the initialization voltage line, and including a second-first switch element connected to a second-first gate line and a second-second switch element connected to a second-second gate line, and the first-second gate line and the second-first gate line are electrically connected.

A display device including: a display panel which includes a plurality of pixels, and outputs image data in an active section of a frame, and does not output image data in a blank section of the frame; and a backlight unit configured to irradiate the display panel with light, wherein a length of the blank section is variable, and the backlight unit is configured to irradiate the display panel with strobe light at the active section, and is configured to irradiate the display panel with a first flat light at the blank section.

Systems and methods for managing refresh rates of applications running on a display device are disclosed. A computing device is designed to monitor and slow/reduce refresh rates for some applications running on the display device, while also allowing other applications to run at a fast/increased refresh rate. Each application is associated with a target device (e.g., server). The computing device can regulate a continuous stream of data, allowing some applications to access the data, while limiting/preventing other applications from accessing the data. The applications with access to the data can run at the fast refresh rates, while the remaining applications update at the slow refresh rates. As a result, the applications running at the fast refresh rates allow a user viewing the display device to actively monitor the respective servers associated with the fast-running applications, while reducing network load based on the relatively slow-running applications.

A display system supports variable refresh rates that include a plurality of refresh rates. A source such as a graphics processing unit (GPU) provides frames to the display system at a selected one of the refresh rates. The refresh rates are factored into a corresponding plurality of prime factors. A plurality of numbers of lines per frame in frames provided at the plurality of refresh rates is determined based on one or more ratios of the plurality of refresh rates, the plurality of prime factors, and a line rate for providing frames to the display system at the plurality of refresh rates. The source then selectively provides frames to the display system at one refresh rate of the plurality of refresh rates using the same line rate regardless of which refresh rate is chosen. Furthermore, the number of lines per frame is an integer for frames provided at the refresh rates.