A display device includes a light emitting element including an anode, a cathode, and a light emitting layer between the anode and the cathode, a first transistor connected between the anode and a first power line, the first transistor may be switched by a voltage of a node, a second transistor connected between the first transistor and a data line, the second transistor may be switched by a write scan signal, a third transistor connected between the node and the anode, the third transistor may be switched by a compensation scan signal, a fourth transistor connected between the node and an initialization line, the fourth transistor may be switched by an initialization scan signal, an insulating layer on the first to the fourth transistors, and a light blocking pattern protruding from the insulating layer, the light blocking pattern being adjacent to the third transistor and the fourth transistor.

The present invention provides a chipset for FRC, wherein the chipset includes a first FRC chip and a second FRC chip. The first FRC chip is configured to receive a first part of input image data, and perform a motion compensation on the first part of the input image data to generate a first part of an output image data, wherein a frame rate of the output image data is greater than or equal to a frame rate of the input image data. The second FRC chip is configured to receive a second part of the input image data, and perform the motion compensation on the second part of the input image data to generate a second part of the output image data; wherein the first part and the second part of the output image data are combined into the complete output image data for displaying on a display panel.

A display panel and a display device are provided. The display panel includes a pixel circuit; and a light-emitting element. The operation process of the pixel circuit includes a first data refresh period, a data adjustment stage, and a second data refresh period set in sequence. The data adjustment stage includes T1 first sub-data adjustment stages set in sequence and T2 second sub-data adjustment stages set in sequence. A quantity of the data writing frames in the first sub-data adjustment stage is greater than a quantity of the data writing frames in the second sub-data adjustment stage. A quantity of the holding frames in the first sub-data adjustment stage is smaller than a quantity of the holding frames in the second sub-data adjustment stage.

A display device includes a display panel including a first partial panel region and a second partial panel region, and a panel driver which drives the display panel. The panel driver determines a first driving frequency for the first partial panel region and a second driving frequency for the second partial panel region. In a case where the first driving frequency and the second driving frequency are different from each other, the panel driver sets a boundary portion including a boundary between the first partial panel region and the second partial panel region, and determines a third driving frequency for the boundary portion to be between the first driving frequency and the second driving frequency.

An image display system includes a graphic processor which generates an image signal, a control signal, and a variable frequency signal; and a display device which displays an image at a frame frequency corresponding to the variable frequency signal from the graphic processor. The display device includes pixels connected to emission control lines, data lines, and scan lines; a controller which provides reference data including information on reference cycles, which are cycles in which an emission control start signal is output, to the graphic processor, outputs the emission control start signal based on the control signal, and adjusting an output timing of a scan start signal based on the variable frequency signal; an emission driver which supplies emission control signals to the emission control lines based on the emission control start signal; and a scan driver which supplies scan signals to the scan lines based on the scan start signal.

The present disclosure relates to the technical field of display panels, in particular to a driving method and driving apparatus of a display panel. The driving method may include in response to detecting that the display panel is switched from a dynamic picture to a static picture, generating a refresh rate adjustment instruction; according to the refresh rate adjustment instruction, switching the picture refresh rate of the display panel from a first picture refresh rate to a second picture refresh rate and generating a voltage adjustment instruction; obtaining a target cathode power supply voltage matching the second picture refresh rate; and based on the voltage adjustment instruction and the target cathode power supply voltage, adjusting the display panel to change a working current of each pixel in the display panel.

A display device includes: a pixel unit having a plurality of pixels; a timing controller supplying respective scan start signals to a plurality of scan drivers and an emission start signal to an emission driver, in response to synchronization signals supplied from the outside; the emission driver supplying an emission signal to emission control lines connected to the pixels based on the emission start signal; the scan drivers supplying scan signals to the scan lines connected to the pixels based on the scan start signal; and a data driver supplying a data signal to data lines connected to the pixels, and at least one of a frequency of the emission start signal and frequencies of the scan start signals may be a first frequency that is determined independently of a driving frequency when the driving frequency is less than or equal to a threshold value.

A signal processing method includes: obtaining a first frame synchronization signal including a plurality of first pulses, a period between a trailing edge of a first pulse and a leading edge of a next first pulse being a first time period, which corresponding to a first integer number of pulses of a first pixel clock signal; generating a synchronization calibration signal including a plurality of second pulses, a trigger edge of each second pulse being at a same time as the trailing edge of the first pulse; and generating a second frame synchronization signal including a plurality of third pulses, a period between the trigger edge of each second pulse and a leading edge of a third pulse closest to the second pulse after the second pulse being a second time period, which corresponding to a first integer number of pulses of the second pixel clock signal.

A display device dynamically determines pixel settle times to reduce a display latency. The display device includes a backlight unit (BLU) for providing light for displaying an image, a plurality of pixels for modulating the light provided by the BLU, and a controller circuit for controlling the BLU and the plurality of pixels. The controller circuit determines a settle time from display data for a current display frame and display data for a previous display frame, and turns on the BLU based on the determined settle time. The determined settle time corresponding to an expected amount of time for the plurality of pixel to transition from a first state corresponding to the display data for the previous display frame to a second state corresponding to the display data for the current display frame.

A compositor receives, from each of a plurality of originating devices, compressed and/or encrypted image data portions of a frame of image data, together with portion metadata for each of the compressed and/or encrypted image data portions. Frame metadata for the frame of image data. The compositor then composites the image data portions without decompressing and/or decrypting them, based on the portion and frame metadata, by generating composited frame metadata for the composited image frame and amending the portion metadata for each of the compressed and/or encrypted image data portions to indicate a location of the compressed and/or encrypted image data portions in the composited image frame. The compressed and/or encrypted image data portions, the composited frame metadata and the amended portion metadata are then transmitted by the compositor to a display control device.