An electronic appliance is provided. The electronic appliance includes a communication interface, a memory storing at least one instruction, and a processor which is connected with the memory and the communication interface and controls the electronic apparatus. Here, the processor may, by executing the at least one instruction, based on an event for reading extended display identification data (EDID) stored in the memory at an external apparatus connected through the communication interface occurring, toggle a first signal related to the communication interface, and after the first signal is toggled, monitor a signal output from the external apparatus and identify whether the external apparatus failed to read the EDID information, and based on identifying that the external apparatus failed to read the EDID information, toggle a second signal related to the communication interface.

A transceiver system includes a transmitter including a first driving signal output unit and a second driving signal output unit and a receiver including a first sensing signal input unit and a second sensing signal input unit. A first channel includes a first input/output line and a second input/output line that connect the first driving signal output unit and the first sensing signal input unit, and are configured to transfer signals having different phases; a second channel including a third input/output line and a fourth input/output line that connect the second driving signal output unit and the second sensing signal input unit, and are configured to transfer signals having different phases; and a first compensation capacitor including a first electrode electrically connected to the second input/output line and a second electrode electrically connected to the third input/output line.

A tiling display apparatus includes a set board configured to generate a control command signal and a plurality of display modules connected to one another through a first interface circuit based on a serial communication scheme, for executing a target operation corresponding to the control command signal, and the first interface circuit is implemented with a bidirectional serial interface having a feedback loop type between adjacent display modules of the plurality of display modules.

A display substrate has a display area and a peripheral area around the display area. The display substrate includes a plurality of sub-pixels arranged in an array in the display area, and an interface circuit, at least two serial-to-parallel converters and at least one display driver that are in the peripheral area. The interface circuit is configured to receive target data including a plurality of serial display data. A serial-to-parallel converter in the at least two serial-to-parallel converters is used to convert the plurality of serial display data into parallel display data. The serial-to-parallel converter is electrically connected to one display driver to provide the parallel display data to the display driver. The display driver is used to output display driving signals to a plurality of sub-pixels according to the parallel display data.

A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1-1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1-1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.

The present disclosure relates to a data driving device, a data processing device, and a system for driving a display device and, more particularly, it relates to a data driving device, a data processing device, and a system for smoothly performing a low-speed communication through a communication line including an alternating current coupling capacitor.

Methods, systems and devices for displaying video content on large, high resolution video walls, which may comprise a mesh network of an array of display tiles with redundant network switching, in which a virtual, unlimited pixel canvas is created in a video controller memory to facilitate packetizing and addressing of video content packets for delivery to the video wall through a packet-switched network. Embodiments disclosed are particularly well-suited for use with video walls employing LED tiles.

The present disclosure relates to a data driving device, a data processing device, and a system for driving a display device and, more particularly, it relates to a data driving device, a data processing device, and a system for smoothly performing a low-speed communication through a communication line including an alternating current coupling capacitor.

An electronic device is provided. The electronic device includes a communication circuit, and at least one processor operatively connected to the communication circuit, wherein the at least one processor is configured to establish, via the communication circuit, a communication connection with a display device, identify channel information about a first channel on which the communication connection is established, identify image information about an image displayed in the display device, and based on the channel information about the first channel and the image information, identify whether the electronic device is capable of transmitting a data frame each communication cycle which corresponds to a frame rate provided in the display device.

A caption encoder system is provided that can include a computer system and a caption encoder card. The caption encoder card can include a caption encoder module having at least one of: an input component, a field programmable gate array (FPGA), a microcontroller unit (MCU), a peripheral component interconnect express (PCIe) bridge, and a plurality of output components. The input component can be configured to receive an input SDI stream. The FPGA can be in communication with the input component and can be configured to compile an output SDI stream with embedded closed captions. The MCU can be in communication with the FPGA. The PCIe bridge can be in communication with the microcontroller unit and a plurality of universal serial bus to serial devices. The plurality of output components can be communication with the field programmable gate array.