A display device including pixels; a controller configured to generate first compensation data based on first sensing data with respect to threshold voltages of driving transistors of the pixels which are sensed during a first sensing period, to generate second compensation data based on second sensing data with respect to mobilities of the driving transistors of the pixels which are sensed during the first sensing period, to generate third compensation data based on third sensing data with respect to mobility change amounts of the driving transistors of the pixels which are sensed using image data for sensing compensated based on the first and second compensation data during a second sensing period, and to compensate input image data based on the first, second, and third compensation data to generate compensated image data; and a data driver configured to provide data voltages to the pixels based on the compensated image data.

Disclosed is a display device which includes a display panel that includes a plurality of pixels and includes a display area displaying an image, a panel controller that receives an external input signal from an external source and generates a control signal for dividing the display area into a first area and a second area which is disposed adjacent to the first area based on the external input signal, and an instrument module that stretches the first area and the second area of the display panel in response to the control signal. The number of the pixels per unit area in the first area is different from the number of the pixels per unit area in the second area.

A display driver integrated circuit includes a gamma circuit, a control circuit, and an output buffer circuit. The gamma circuit generates a plurality of gamma voltages based on gamma control information, a first gamma power supply voltage and a second gamma power supply voltage. The control circuit calculates a gamma limit value based on panel brightness information, voltage levels of the first and second gamma power supply voltages and the number of the plurality of gamma voltages. The control circuit generates a mode determination signal. The output buffer circuit includes a plurality of buffer circuits. Each of the plurality of buffer circuits includes an input stage and the input stage includes first transistors and second transistors. In a first driving mode, each of the plurality of buffer circuits turns off the first transistors and turns on the second transistors included in the input stage.

An apparatus is disclosed for bidirectional amplification with phase-shifting. In example implementations, an apparatus includes a phase shifter with a bidirectional amplifier. The bidirectional amplifier includes a first transistor coupled between a first plus node and a second minus node, a second transistor coupled between a first minus node and a second plus node, a third transistor coupled between the first plus node and the second minus node, and a fourth transistor coupled between the first minus node and the second plus node. The bidirectional amplifier also includes a fifth transistor coupled between the first plus node and the second plus node, a sixth transistor coupled between the first minus node and the second minus node, a seventh transistor coupled between the first plus node and the second plus node, and an eighth transistor coupled between the first minus node and the second minus node.

This application provides an electronic device, to reduce a probability that a screen stalling phenomenon. A timing control unit sends one first pulse of a tearing effect signal every a first preset time T1. The timing control unit sends S second pulses of the tearing effect signal when a transceiver unit does not receive an N.sup.th frame of display data within a preset time. The processing unit receives the N.sup.th frame of display data in the (N+1).sup.th frame, and controls, based on the N.sup.th frame of display data, the display to display an N.sup.th frame of image.

A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and a data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.

A display device including: a display panel including first and second display areas, and including pixels in the first and second display areas; and a data driver to output data signals to the pixels through a channels arranged along a first direction, wherein the channels include a first channel group corresponding to the first display area and a second channel group corresponding to the second display area, wherein some of the pixels emit light in different colors and have a first pixel arrangement along the first direction, and based on channel selection information about the first or second channel groups, the data driver outputs first data signals in a first output order along the first direction corresponding to the first pixel arrangement through the first channel group, and outputs second data signals in a second output order different from the first output order through the second channel group.

A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Display device including: a pixel matrix comprising a plurality of pixel groups, each group comprising a plurality of pixel blocks; a video card comprising an input configured to receive a digital signal to be displayed, and a plurality of outputs each coupled to a group by an associated primary data distribution network, the video card being configured to decode the digital signal and send to each of the outputs of digital data encoded in a format suitable for the matrix and intended to be displayed by the group coupled to said output; and wherein: each group includes a plurality of control circuits each associated with a block of the group and coupled to the associated main data bus; each pixel includes a driver circuit configured to generate pixel control signals.

A display device includes a display panel, a data driver which provides data voltages to the display panel, and a controller which provides output image data to the data driver. The controller includes a data line memory which stores input image data for each pixel row of the display panel, an address line memory which stores addresses for the input image data, and a data serialize block which generates the output image data provided to the data driver by rearranging the input image data stored in the data line memory based on the addresses stored in the address line memory.