In some embodiments, systems, devices, and methods are provided that allow a host device to communicate video information, network information, and USB information over USB via a USB host controller. The video information and the network information are encapsulated within USB and communicated by the USB host controller.

In some embodiments, the USB information communicated by the USB host controller is further communicated over a non-USB extension medium by an upstream facing port device and one or more downstream facing port devices.

A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

A transceiver system includes a transmitter including a first driving signal output unit and a second driving signal output unit and a receiver including a first sensing signal input unit and a second sensing signal input unit. A first channel includes a first input/output line and a second input/output line that connect the first driving signal output unit and the first sensing signal input unit, and are configured to transfer signals having different phases; a second channel including a third input/output line and a fourth input/output line that connect the second driving signal output unit and the second sensing signal input unit, and are configured to transfer signals having different phases; and a first compensation capacitor including a first electrode electrically connected to the second input/output line and a second electrode electrically connected to the third input/output line.

A the display panel includes a plurality of sub-pixels arranged in rows and columns; one scan line disposed in each of the rows of the plurality of sub-pixels; two data lines are disposed in each of the columns of the plurality of sub-pixels; a first multiplexer configured to select a data line at one side among the two data lines disposed in each column; and a second multiplexer configured to select a data line at another side among the two data lines disposed in each column that can be operated at a high speed using a 2D1G structure as well as at a low speed in an interlace scheme, thus securing 2H sensing time and removing flickering during switching between operations of pixels.

A display panel and a driving method thereof are provided, including a time schedule controller and at least one driver integrated circuit (driver IC). Pulse width modulation (PCM) data between the time schedule controller and the driver IC is transmitted in a decoded manner, and pulse amplitude modulation (PAM) data is transmitted in an undecoded manner, reducing a transmission rate between the time schedule controller and the driver IC, and thereby reducing or eliminating risks of electromagnetic interference (EMI). Furthermore, using this transmission method can reduce the number of latches used in the driver IC.

The present disclosure relates to a data transmission and reception method of a data driving device and a data processing device as well as a data transmission and reception system, and more particularly, to a method and a system in which the data driving device receives an initial configuration value from the data processing device, stores the initial configuration value as a configuration restoration value, and rapidly restore an environment for a high-speed communication by using the stored configuration restoration value when a link between the data processing device and the data driving device is lost so as to reduce a time for restoration.

An interface circuit comprises a timing signal generating unit that generates a timing signal indicating a timing to switch between a data input period and a non-input period, a plurality of driver error detection circuits that detects an error in source drivers, a selector circuit that selects one of the driver error detection circuits in the non-input period and that outputs a driver error detection signal indicating an error detection result, an input error detection circuit that detects an input error of a data signal and outputs an input error detection signal indicating the result, an OR circuit that outputs an OR of the driver error detection signal and the input error detection signal, and a signal output unit connected to an output part of the OR circuit.

The present disclosure relates to a data processing device, a data driving device, and a system for driving a display device, and more particularly, to a data processing device, a data driving device, and a system capable of reducing power consumption of the display device.

It is an object to realize a correcting process for correcting a defective image in a region of interest (ROI) that is a partial region segmented from a captured image. A transmitting apparatus includes a controlling section that controls the holding of defect correcting information for use in correcting a defect in an image included in a ROI and a transmitting section that sends out image data of the image included in the ROI as payload data and sends out ROI information as embedded data.

A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.