A method of reading data includes: receiving a digital signal, wherein the digital signal includes a sync signal and a data signal; performing an oversampling operation to the digital signal, and calculating a plurality of sampling points according to the oversampling operation; by a first counter counting the sampling points to obtain a first count value; based on the first count value defining a second count value; defining a unit interval; in the unit interval, defining a data reading range; and in the data reading range, reading the data signal corresponding to data of the unit interval as a first value when a potential of each of the sampling points counted is changed from a first potential to a second potential.

A display device and a driving circuit are discussed. According to an embodiment of the present disclosure, it is possible to stably maintain the output signal of the driving circuit when the lock signal indicating the synchronization state of the clock signal is changed due to an operation error such as overcurrent in a display device using a point-to-point interface. In addition, according to an embodiment of the present disclosure, it is possible to prevent damage to the display panel due to an overload generated in the output signal of the driving circuit by an operation error. In addition, according to an embodiment of the present disclosure, it is possible to prevent overload of the driving circuit and damage to the display panel by controlling the operation of the driving circuit through a differential input voltage between the timing controller and the driving circuit.

A display device may include a display panel including a gate line, a data line, and a pixel electrically connected to the gate line and the data line, where display panel displays an image based on input image data, a gate driver which outputs a gate signal to the gate line, a data driver which outputs a data voltage to the data line, and a power supply voltage generator which provides a driving voltage to the display panel, the gate driver and the data driver. The power supply voltage generator generates a gate clock signal based on an on-clock signal and an off-clock signal and changes a count value of the on-clock signal or the off-clock signal when the gate clock signal is an abnormal signal.

A signal is transmitted at a high speed in a direction opposite to a transmitting direction of a main large-capacity channel. A first transmitting unit transmits a first signal including a clock component to an external device through a transmission path as a differential signal. A second transmitting unit superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the external device. A state notifying unit communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.

A display device includes a pixel unit including first pixels disposed in a first area and second pixels disposed in a second area, an emission driver configured to sequentially supply emission signals of a turn-off level to the first pixels and the second pixels based on a first start signal, a first clock signal, and a second clock signal, and a first scan driver configured to sequentially supply first scan signals of a turn-on level to the first pixels based on a second start signal, the first clock signal, and the second clock signal, and sequentially supply the first scan signals of the turn-on level to the second pixels based on a third start signal, the first clock signal, and the second clock signal.

In some embodiments, an apparatus comprises a media module and a modification module included in an embedded appliance. The media module is configured to receive a first media signal associated with a first input port of the embedded appliance and a second media signal associated with a second input port of the embedded appliance. The media module is configured to identify a first set of media signal parameters based on the first media signal. The modification module is configured to receive a modification instruction associated with a session format having a second set of media signal parameters different from the first set of media signal parameters. The modification module is configured to modify the first media signal based on the first set of media signal parameters and the modification instruction to produce a first modified media signal in the session format and having the second set of media signal parameters.

A timing controller of a display set is integrated with an encoder for transport of analog signals between a display controller and source drivers of the display panel. The timing controller and integrated encoder are within an integrated circuit and are part of a chipset. The integrated circuit is located immediately after the SoC of a display set or is integrated within the SoC. A video signal sent to the timing controller chip is unpacked into sample values which are permuted into vectors of samples, one vector per encoder. Each vector is converted to analog, encoded and the analog levels are sent to the source drivers which decode into analog samples. Or, each digital vector is encoded and then converted to analog. A line buffer uses a memory to present a row of pixel information to the encoders. A mobile telephone has an integrated TCON with SSVT transmitter.

The present disclosure relates to a data transmission and reception method of a data driving device and a data processing device as well as a data transmission and reception system, and more particularly, to a method and a system in which the data driving device receives an initial configuration value from the data processing device, stores the initial configuration value as a configuration restoration value, and rapidly restore an environment for a high-speed communication by using the stored configuration restoration value when a link between the data processing device and the data driving device is lost so as to reduce a time for restoration.

Embodiments of the disclosure relate to a control circuit, a display device, and a method for driving a main processor. Specifically, there may be provided a control circuit, a display device, and a method for driving a main processor which may reduce power consumption in the transmission/reception circuit connected with the interface by powering off at least one of the source transmission/reception circuit or sink transmission/reception circuit electrically connected with the auxiliary channel AUX during at least a partial period of the vertical blank period.

A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.