Disclosed herein is a method of writing data to, and reading data from, one or more buffers. The method comprises: determining a write rate of writing data into a first buffer; determining a read rate of reading data from the first buffer; determining, using the write rate and the read rate, a portion of the first buffer; writing data into the portion of the first buffer; starting to read data from the first buffer when the writing of data to the portion of the first buffer has finished; and writing data into a remaining part of the first buffer, different from the portion of the first buffer. The portion of the first buffer is determined such that the reading of data from the first buffer does not overtake the writing of data into the first buffer.

A novel image processing method is provided. In a display device in which a video signal is individually supplied to a screen divided into two, the entire screen is subjected to up-conversion processing after being divided, and another up-conversion processing is performed for a boundary portion of the screen divided into two. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion are performed in parallel with the use of a plurality of arithmetic units. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion can be performed using different algorithms.

A novel image processing method is provided. In a display device in which a video signal is individually supplied to a screen divided into two, the entire screen is subjected to up-conversion processing after being divided, and another up-conversion processing is performed for a boundary portion of the screen divided into two. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion are performed in parallel with the use of a plurality of arithmetic units. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion can be performed using different algorithms.

An electronic display may include a pixel circuit. The pixel circuit may include memory storage to store data values representative of image data to be depicted via the pixel circuit. The memory storage may also include memory components for storing bits of the data value. The pixel circuit may also include a light-emitting device for emitting light based at least in part on the data value and a controller. The controller may receive the data value and store the bits based on a mapping between the bits and the memory components. The mapping may be determined based on routing one or more of the bits associated with one or more defective memory components of the memory components to one or more other memory components of the memory components. The controller may also drive the light-emitting device to emit light based on the bits stored in accordance with the mapping.

An electronic display may include a pixel circuit. The pixel circuit may include memory storage to store data values representative of image data to be depicted via the pixel circuit. The memory storage may also include memory components for storing bits of the data value. The pixel circuit may also include a light-emitting device for emitting light based at least in part on the data value and a controller. The controller may receive the data value and store the bits based on a mapping between the bits and the memory components. The mapping may be determined based on routing one or more of the bits associated with one or more defective memory components of the memory components to one or more other memory components of the memory components. The controller may also drive the light-emitting device to emit light based on the bits stored in accordance with the mapping.

Disclosed are a vector diagram generation method and apparatus, and a storage medium, the method being used in an FPGA. The method comprises: acquiring video data of an ultra-high definition video system; on the basis of the video data, generating vector diagram data; acquiring a pre-generated background image of the vector diagram; and, on the basis of the background image and the vector diagram data, generating a vector diagram. The vector diagram generation method and apparatus and storage medium provided in the present disclosure can better implement vector diagram generation of the ultra-high definition video system. (FIG. 1)

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

Embodiments disclosed herein relate to device and method for processing frames. For example, a buffer of a device is arranged to store a plurality of rendered frames rendered at a frame rendering rate and a time stamp for each of rendered frames. A compositor of a device is arranged to obtain a timestamp of a synchronisation signal for synchronising the display of frames with a display refresh rate. In response to obtaining a timestamp of a synchronisation signal, a compositor is arranged to trigger access to a buffer to obtain two rendered frames having timestamps closest to a timestamp of a synchronisation signal. An interpolator of a device is arranged to generate an interpolated rendered frame for display by performing an interpolation operation using two rendered frames. An interpolation operation takes into account the difference between timestamps of each of two rendered frames and a timestamp of a synchronisation signal.

An apparatus includes a graphics driver circuit and a graphics engine circuit. The graphics engine circuit is configured to determine graphics data to be output to a display and to render the graphics data to a buffer. The graphics driver circuit is configured to output the buffer to the display. The graphics engine circuit is further configured to, while the graphics driver circuit is outputting the first buffer to the display, encode the first graphics data into another buffer, and to signal the graphics driver circuit to output the other buffer to the display.