According to one embodiment, a magnetic disk device includes a disk, a head including a main pole configured to apply a recording magnetic field to the disk, and side shields provided in a first direction with respect to the main pole and possessing a magnetic field in the magnetization direction of the first direction, and a controller configured to output a recording current in which a magnitude of a first electric current and a magnitude of a second electric current opposite to the first electric current in direction of the current are different from each other to the head according to the magnetic field of the side shields.

A data delay circuit, for delaying a portion of a data signal for application to a write head of a hard disk drive, includes a data delay cell including two inverters and a charge current source for charging at least one of the inverters, and a bias circuit for programming delay of the data delay cell. The bias circuit is in current-mirroring relationship with the charge current source and includes a current-based digital-to-analog converter (DAC) for programmably selecting the delay of the data delay cell, and a reference current source for the DAC. The data delay cell and the bias circuit are subject to gain error, and the data delay circuit further includes compensation circuitry for reducing the effect of the gain error. The compensation circuitry may include replica charge current and reference current sources that are fed back through a gain cell.

A hard disk drive write drive method and integrated circuit that provide a configurable overshoot current based on the length of the pattern in the write current signal that is being written to the hard disk by the write driver. The hard disk write driver adds a first overshoot current to all patterns in the write current signal and adds an additional second overshoot current to patterns in the write current signal shorter than a first duration. The hard disk drive write driver utilizes an H-bridge circuit configured to add the first overshoot current and the additional second overshoot current to the write current signal. The H-bridge circuit is comprised of four switching elements that are configured to generate a first overshoot current for all pattern transitions of the write current signal and generate a second overshoot current for pattern transitions shorter than the first duration.

A hard disk drive write drive method and integrated circuit that provide a configurable overshoot current based on the length of the pattern in the write current signal that is being written to the hard disk by the write driver. The hard disk write driver adds a first overshoot current to all patterns in the write current signal and adds an additional second overshoot current to patterns in the write current signal shorter than a first duration. The hard disk drive write driver utilizes an H-bridge circuit configured to add the first overshoot current and the additional second overshoot current to the write current signal. The H-bridge circuit is comprised of four switching elements that are configured to generate a first overshoot current for all pattern transitions of the write current signal and generate a second overshoot current for pattern transitions shorter than the first duration.

An apparatus including a current source. The current source divides a current from a voltage supply into current streams in response to converting a voltage from a voltage supply into a plurality of current streams. The current source modulates a current streams with signals to convert the current streams into first and second current streams. The current source combines the first and second current streams into a single current stream and supplies the single current stream to a load in a flow direction.

A module including first and second variable inductances. The first variable inductance is electrically connected to a pair of nodes in a first half-circuit. One of the nodes in the first half-circuit is a first connection terminal. The second variable inductance is electrically connected to a pair of nodes in a second half-circuit. One of the nodes in the second half-circuit is a second connection terminal. The first half-circuit receives a flow of current in response to the second half-circuit supplying the current to the load in a flow direction from a load through the first connection terminal. The second half-circuit is configured to receive the flow of the current in response to the first half-circuit supplying the current to the load in a direction opposite to the flow direction from the load through the second connection terminal.

An apparatus including a current source. The current source divides a current from a voltage supply into current streams in response to converting a voltage from a voltage supply into a plurality of current streams. The current source modulates a current streams with signals to convert the current streams into first and second current streams. The current source combines the first and second current streams into a single current stream and supplies the single current stream to a load in a flow direction.

According to an embodiment, a circuit for reducing current transition times includes a pre-biased first transistor, a second transistor, and a binary-weighted capacitor network with selectively activated capacitors controlled by logic gates receiving a command signal and boost selection signals. A resistor between the transistors provides a voltage restoration path. Another embodiment includes a binary-weighted resistor network with parallel resistor paths and switches. A write driver system incorporates the boost circuits, arranged in diagonal pairs across a bridge circuit. A control circuit activates the diagonal boost circuit pairs during switching transitions of the bridge circuit, generating current pulses that combine with the main bridge current to reduce transition times at a magnetic recording head while maintaining impedance matching. The boost circuits enable programmable current levels and sub-nanosecond pulse durations without complex timing circuitry, enhancing write performance in magnetic recording systems.