A method is performed at an electronic device that includes magnetic random access memory (MRAM). The method includes loading the MRAM with data including main data, first error correcting data, and second error correcting data. The MRAM comprises a plurality of MRAM cells characterized by a first magnetic anisotropy corresponding to a first error rate at a predefined temperature that exceeds a threshold for correcting errors using only the first error correcting data. The method further includes, after loading the MRAM with the data, heating the MRAM to the predefined temperature and correcting errors in the main data using both the first error correcting data and the second error correcting data. The method further includes after correcting the errors in the main data, erasing, from the MRAM, the second error correcting data and maintaining, on the MRAM, the first error correcting data.

An aspect includes data backup management between volatile memory and non-volatile memory in a through-silicon via module of a computer system. Data is copied data from the volatile memory to the non-volatile memory during a refresh cycle of the volatile memory. The data is written to one or more non-volatile memory cells within the non-volatile memory prior to a next refresh cycle of the volatile memory.

An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit.