Disclosed are a 3D non-volatile memory, an operating method thereof, and a manufacturing method thereof. The 3D non-volatile memory includes a bit line formed to extend in a vertical direction and horizontal structures contacting the bit line while being formed to extend in a horizontal direction and being space in the vertical direction. Each of the horizontal structures includes a ferroelectric layer contacting the bit line, a middle metal layer surrounded by the ferroelectric layer, a dielectric layer surrounded by the middle metal layer, and a word line surrounded by the dielectric layer.

A sub-sense amplifier includes a semiconductor substrate, a first pair of complementary transistors, a second pair of complementary transistors, and at least one ground transistor. The first pair and second pair of complementary transistors and the ground transistor are formed on the semiconductor substrate. The first pair of complementary transistors are disposed in line symmetry with a center line of the sub-sense amplifier as a symmetry axis, and gates of the first pair of complementary transistors are coupled to a node. The second pair of complementary transistors are also disposed in line symmetry with the center line, wherein the current directions of the second pair of complementary transistors are the same. Sources and drains of the first pair of complementary transistors are coupled to gates and sources of the second pair of complementary transistors, respectively. The ground transistor connects in series with the second pair of complementary transistors.

A ferroelectric memory circuit (100) includes: a memory cell (102), wherein a memory state (102s) of the memory cell (102) is switchable between a first memory state and a second memory state, the memory cell (102) further configured to output an electrical current (101) in response to receiving a readout voltage (103); and a sense circuit (104) configured to output an output voltage (105) based on the result of integrating the electrical current (101) output by the memory cell (102), wherein the output voltage (105) represents whether the memory state (102s) is the first memory state or the second memory state.

Methods, systems, and devices for inductive energy harvesting and signal development for a memory device are described. One or more inductors may be included in or coupled with a memory device and used to provide current for various operations of the memory device based on energy harvested by the inductors. An inductor may harvest energy based on current being routed through the inductor or based on being inductively coupled with a second inductor through which current is routed. After harvesting energy, an inductor may provide current, and the current provided by the inductor may be used to drive access lines or otherwise as part of executing one or more operations at the memory device. Such techniques may improve energy efficiency or improve the drive strength of signals for the memory device, among other benefits.

Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.

In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect wires and vias arranged within one or more interconnect dielectric layers over a substrate. Further, a bottom electrode is disposed over the one or more interconnect wires and vias and comprises a first material having a first work function. A top electrode is disposed over the bottom electrode and comprises a second material having a second work function. The first material is different than the second material, and the first work function is different than the second work function. An anti-ferroelectric layer is disposed between the top and bottom electrodes.

Some embodiments include a ferroelectric transistor having a conductive gate structure, a first ring extending around the conductive gate structure and a second ring extending around the first ring. The first ring includes ferroelectric material. The second ring includes insulative material. A mass of channel material is outward of the second ring. Some embodiments include integrated assemblies and methods of forming integrated assemblies.

Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.