Some embodiments include a ferroelectric transistor having a conductive gate structure, a first ring extending around the conductive gate structure and a second ring extending around the first ring. The first ring includes ferroelectric material. The second ring includes insulative material. A mass of channel material is outward of the second ring. Some embodiments include integrated assemblies and methods of forming integrated assemblies.

Some embodiments include a ferroelectric transistor having a conductive gate structure, a first ring extending around the conductive gate structure and a second ring extending around the first ring. The first ring includes ferroelectric material. The second ring includes insulative material. A mass of channel material is outward of the second ring. Some embodiments include integrated assemblies and methods of forming integrated assemblies.

Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.

Methods, systems, and devices for cell data bulk reset are described. In some examples, a logic state (e.g., a first logic state) may be written to one or more memory cells based on an associated memory device transitioning power states. To write the first logic state to the memory cells, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage. In some instances, the word lines may be driven to the second voltage based on charge sharing occurring between adjacent word lines.

A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.

Various aspects relate to a memory cell arrangement including: a field-effect transistor based capacitive memory cell including a memory element, wherein a memory state of the memory element defines a first memory state of the field-effect transistor based capacitive memory cell and wherein a second memory state of the memory element defines a second memory state of the field-effect transistor based capacitive memory cell; and a memory controller configured to, in the case that a charging state of the field-effect transistor based capacitive memory cell screens an actual threshold voltage state of the field-effect transistor based capacitive memory cell, cause a destructive read operation to determine whether the field-effect transistor based capacitive memory cell was, prior to the destructive read operation, residing in the first memory state or in the second memory state.

Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.

Various aspects relate to a memory cell arrangement including: a memory cell including a field-effect transistor structure and a spontaneous-polarizable memory layer; and a control circuit configured to cause a writing of the memory cell by a writing operation, the writing operation including: carrying out a writing sequence including: supplying a write signal set to the memory cell to provide a write voltage drop to bring a threshold voltage of the memory cell into a target range by polarizing the memory layer, and, subsequently, supplying a post-conditioning signal set to the memory cell to provide a post-conditioning voltage drop having opposite polarity with respect to the write voltage drop to change the threshold voltage by partially depolarizing the memory layer; and checking whether the threshold voltage is in the target range, and repeating the writing sequence in the case that the threshold voltage is not in the target range.

Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.

A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted.