A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

A device, a memory interface device, and a method of implementing an active inductor circuit are disclosed. In one aspect, the device includes one or more active inductor circuits, each including a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The first MOS transistor has a first terminal connected to a first voltage level, a second terminal connected to a resistor, and a gate terminal. The second MOS transistor has a first terminal connected to the first voltage level, a second terminal connected to a first current source and the gate terminal of the first MOS transistor, and a gate terminal connected to the resistor and to a capacitor connected to a second voltage level. One of the first MOS transistor and the second MOS transistor is a p-channel MOS (PMOS) transistor, and another of the first MOS transistor and the second MOS transistor is an n-channel MOS (NMOS) transistor.

A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

A semiconductor device includes a substrate provided with a decoupling capacitor and plurality of circuit elements disposed along a first direction, and a plurality of first wiring line patterns disposed in a first wiring line layer over the substrate, including a power routing pattern coupled to the decoupling capacitor and a plurality of internal wiring line patterns coupled to the plurality of circuit elements. The plurality of first wiring line patterns extend in the first direction, and are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting the first direction and parallel to the substrate.

A semiconductor device includes a substrate provided with a decoupling capacitor and plurality of circuit elements disposed along a first direction, and a plurality of first wiring line patterns disposed in a first wiring line layer over the substrate, including a power routing pattern coupled to the decoupling capacitor and a plurality of internal wiring line patterns coupled to the plurality of circuit elements. The plurality of first wiring line patterns extend in the first direction, and are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting the first direction and parallel to the substrate.

A method includes forming a first transistor, a second transistor, a third transistor, and a fourth transistor over a substrate, wherein at least the second and third transistors include ferroelectric materials; forming an interlayer dielectric (ILD) layer over the first to fourth transistors; forming a first metal line over the ILD layer to interconnect drains of the second and third transistors and a gate of the fourth transistor; forming a second metal line over the ILD layer to interconnect a drain of the first transistor and gates of the second and third transistors; forming a write word line over the ILD layer and electrically connected to a gate of the first transistor but electrically isolated from the fourth transistor; forming a word line over the ILD layer and electrically connected to a source of the first transistor; and forming a bit line electrically connected to the fourth transistor.

A method includes forming a first transistor, a second transistor, a third transistor, and a fourth transistor over a substrate, wherein at least the second and third transistors include ferroelectric materials; forming an interlayer dielectric (ILD) layer over the first to fourth transistors; forming a first metal line over the ILD layer to interconnect drains of the second and third transistors and a gate of the fourth transistor; forming a second metal line over the ILD layer to interconnect a drain of the first transistor and gates of the second and third transistors; forming a write word line over the ILD layer and electrically connected to a gate of the first transistor but electrically isolated from the fourth transistor; forming a word line over the ILD layer and electrically connected to a source of the first transistor; and forming a bit line electrically connected to the fourth transistor.

Provided is a capacitor device, a unit synapse using the capacitor device, a synapse array using the unit synapses. The capacitor device comprises a semiconductor layer which include first and second doping regions formed to be spaced apart from each other and a body region formed between the first and second doping regions; a gate electrode provided above the body region; and a gate insulator stack to have a memory function and disposed between the gate electrode and the semiconductor layer. The capacitance between the gate electrode and the first doping region is determined according to information stored in the gate insulator stack, and the state of the capacitor device is determined according to the capacitance to be one of two preset states. The unit synapse comprises a pair of capacitor devices to perform an XNOR operation.