A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.

A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.

A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.

A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.

A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of memory cells. The memory cell array comprises: a plurality of first conductive layers that are stacked in a first direction above a substrate and extend in a second direction intersecting the first direction; a second conductive layer extending in the first direction; a variable resistance film provided at intersections of the plurality of first conductive layers and the second conductive layer; a first select transistor disposed closer to a side of the substrate than a lowermost layer of the plurality of first conductive layers, the first select transistor including a first select gate line intersecting the second conductive layer; a third conductive layer that extends in a third direction intersecting the second direction and is connected to a lower end of the second conductive layer via the first select transistor; and a second select transistor disposed between at least one pair of the plurality of first conductive layers adjacent in the first direction, the second select transistor including a second select gate line intersecting the second conductive layer.

A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and a page read operation includes a first refresh operation of increasing by an impact ionization phenomenon, a group of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a subsequent second refresh operation of making some of a group of positive holes in the semiconductor body of a memory cell for which page writing has not been performed disappear and decreasing the number of positive holes.

A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and a page read operation includes a first refresh operation of increasing by an impact ionization phenomenon, a group of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a subsequent second refresh operation of making some of a group of positive holes in the semiconductor body of a memory cell for which page writing has not been performed disappear and decreasing the number of positive holes.

A magnetic memory device includes a spin-orbit interaction active core having a number of layers stacked along a longitudinal axis and a magnetic junction extending around the longitudinal axis and substantially surrounding at least a portion of the spin-orbit interaction active core. The magnetic junction includes a free layer, a reference layer, and a tunnel barrier layer between the free layer and the reference layer.

A magnetic memory device includes a spin-orbit interaction active core having a number of layers stacked along a longitudinal axis and a magnetic junction extending around the longitudinal axis and substantially surrounding at least a portion of the spin-orbit interaction active core. The magnetic junction includes a free layer, a reference layer, and a tunnel barrier layer between the free layer and the reference layer.