A qubit memory cell having a thin, optically transparent, metal surface gate that laterally fits into the corresponding region of the memory cell, while not being in direct contact with the perimeter of the region. The surface gate may have apertures to accommodate therein the dot-like control electrodes of the qubit and enable the corresponding electrical overpass bridges to be connected to those dot-like control electrodes. The thickness of the surface gate may be selected such as to let a substantial portion of light impinging thereupon penetrate to the underlying surface of the substrate. In at least some embodiments, the electrical-interconnect structure of the memory cell may be designed to enable separate electrical biasing of the surface gate, e.g., independent of the electrical biasing of some other electrodes of the memory cell. Advantageously, such a surface gate may significantly reduce detrimental clumping of charge carriers in the memory cell.

A qubit memory cell having a thin, optically transparent, metal surface gate that laterally fits into the corresponding region of the memory cell, while not being in direct contact with the perimeter of the region. The surface gate may have apertures to accommodate therein the dot-like control electrodes of the qubit and enable the corresponding electrical overpass bridges to be connected to those dot-like control electrodes. The thickness of the surface gate may be selected such as to let a substantial portion of light impinging thereupon penetrate to the underlying surface of the substrate. In at least some embodiments, the electrical-interconnect structure of the memory cell may be designed to enable separate electrical biasing of the surface gate, e.g., independent of the electrical biasing of some other electrodes of the memory cell. Advantageously, such a surface gate may significantly reduce detrimental clumping of charge carriers in the memory cell.

An electronic device includes a first surface and a second surface opposite the first surface and intended to connect a first electronic component to a second electronic component located on the first surface by at least one conductor track, the conductor track including a plurality of sections disposed one after the other in such a way as to form the conductor track, each section being constituted of a superconducting material chosen in such a way as to form with the section that follows it, if such a section exists, and the section that precedes it, if such a section exists, an acoustic mismatching interface (or Kapitza interface).

An atomic orbital based memory storage is provided that includes a plurality of surface atoms forming dangling bonds (DBs) and a subset of the plurality of surface atoms passivated with spatial control to form covalent bonds with hydrogen, deuterium, or a combination thereof. The atomic orbital based data storage that can be rewritten and corrected as needed. The resulting data storage is also archival and capable of high data densities than any known storage as the data is retained in a binary storage or a given orbital being passivated or a dangling bond (DB). A method of forming and reading the atomic orbital data storage is also provided. The method including selectively removing covalent bonds to form dangling bonds (DBs) extending from a surface atom by hydrogen lithography and imaging the covalent bonds spatially to read the atomic orbital data storage.

An atomic orbital based memory storage is provided that includes a plurality of surface atoms forming dangling bonds (DBs) and a subset of the plurality of surface atoms passivated with spatial control to form covalent bonds with hydrogen, deuterium, or a combination thereof. The atomic orbital based data storage that can be rewritten and corrected as needed. The resulting data storage is also archival and capable of high data densities than any known storage as the data is retained in a binary storage or a given orbital being passivated or a dangling bond (DB). A method of forming and reading the atomic orbital data storage is also provided. The method including selectively removing covalent bonds to form dangling bonds (DBs) extending from a surface atom by hydrogen lithography and imaging the covalent bonds spatially to read the atomic orbital data storage.

Compositions comprising a) one or more amorphous superconductor layers bound to one or more flexible substrate layers, or b) one or more superconductor layers bound to one or more layers of a high dielectric material are disclosed. Furthermore, provided herein are articles comprising one or more compositions of the invention and method of manufacturing thereof.

Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.

Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.

An electronic device includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material includes a first wire and a loop that is (1) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state.

An electronic device includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material includes a first wire and a loop that is (1) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state.